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    Integrated circuit having a multiplying injection-locked oscillator
    21.
    发明授权
    Integrated circuit having a multiplying injection-locked oscillator 有权
    具有倍增注入锁定振荡器的集成电路

    公开(公告)号：US09564911B2

    公开(公告)日：2017-02-07

    申请号：US14858830

    申请日：2015-09-18

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Barry W. Daly ,  Dustin T. Dunwell ,  Anthony Chan Carusone ,  John C. Eble, III

    IPC: H03B27/00 ,  H03L7/24 ,  H03K3/03 ,  H03K5/13

    CPC classification number: H03L7/24 ,  H03B27/00 ,  H03K3/0315 ,  H03K3/0322 ,  H03K5/133 ,  H03K5/1565

    Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

    Abstract translation: 描述了具有乘法注入锁定振荡器的方法和装置。 一些实施例包括脉冲发生器和注射器以及一个或多个注入锁定的振荡器。 脉冲发生器和注射器的输出可以注入到注入锁定振荡器的相应注入点。 在包括多个注入锁定的振荡器的实施例中，每个注入锁定振荡器的输出可以被注入到下一个注入锁定振荡器的相应注入点。 一些实施例通过动态地修改注入锁定振荡器的环路长度和/或通过使用占空比校正器和/或通过复用/混合来自注入锁定振荡器的多个延迟元件的输出来减少确定性抖动。

    JITTER-BASED CLOCK SELECTION
    22.
    发明申请
    JITTER-BASED CLOCK SELECTION 有权
    基于JITTER的时钟选择

    公开(公告)号：US20160233871A1

    公开(公告)日：2016-08-11

    申请号：US15130802

    申请日：2016-04-15

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

    IPC: H03L7/16 ,  H03K3/03 ,  H03L7/24 ,  H03K5/00 ,  H03K5/14

    CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

    Abstract translation: 在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。 在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。 在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。 响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择 时钟。

    Clock recovery circuit
    24.
    发明授权
    Clock recovery circuit 有权

    公开(公告)号：US09209966B1

    公开(公告)日：2015-12-08

    申请号：US14687766

    申请日：2015-04-15

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Jared L. Zerbe ,  Myeong-Jae Park

    IPC: H03D3/24 ,  H04L7/033 ,  H04L7/00 ,  H04L25/03 ,  H03L7/091

    CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/03146 ,  H04L2025/03445

    Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

    METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES
    25.
    发明申请
    METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 有权
    用于设备之间的通道均衡化的不对称分配的方法和电路

    公开(公告)号：US20150349986A1

    公开(公告)日：2015-12-03

    申请号：US14734426

    申请日：2015-06-09

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H04L25/03

    CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

    Integrated circuit comprising a delay-locked loop
    26.
    发明授权
    Integrated circuit comprising a delay-locked loop 有权
    集成电路包括延迟锁定环路

    公开(公告)号：US09160350B2

    公开(公告)日：2015-10-13

    申请号：US13676945

    申请日：2012-11-14

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

    IPC: H03L7/06 ,  H03L7/091 ,  G11C8/18 ,  H03K5/156 ,  H03L7/08 ,  H03L7/081 ,  H03L7/083 ,  H03L7/099 ,  H03L7/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04

    CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

    Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

    Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

    Methods and circuits for asymmetric distribution of channel equalization between devices
    29.
    发明授权
    Methods and circuits for asymmetric distribution of channel equalization between devices 有权
    设备之间信道均衡分配不对称的方法和电路

    公开(公告)号：US09077575B2

    公开(公告)日：2015-07-07

    申请号：US13911363

    申请日：2013-06-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

    USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES
    30.
    发明申请
    USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES 有权
    使用动态脉冲串来支持频率记忆接口

    公开(公告)号：US20150177815A1

    公开(公告)日：2015-06-25

    申请号：US14416088

    申请日：2013-09-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

    Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a START memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

    Abstract translation: 所公开的实施例涉及支持动态突发以促进START存储器控制器和存储设备之间的频率敏捷通信的系统。 在操作期间，系统监视在存储器件和存储器控制器之间的接口处接收到的参考时钟信号。 在检测到从全速率到子速率的参考时钟信号中的频率变化时，接口以突发模式操作，其中数据通过由接口的部分断电的中间的低功率间隔分开的脉冲串传送。

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