公开(公告)号：US20060289988A1

公开(公告)日：2006-12-28

申请号：US11158370

申请日：2005-06-22

Applicant: Vivian Ryan

Inventor： Vivian Ryan

IPC: H01L23/34

CPC classification number: H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract translation: 集成电路管芯包括具有上表面的衬底，形成在衬底的上表面的第一区域中的至少一个有源器件，以及形成在衬底上表面上的至少一个有源器件上的多个层 。 提供了第一层叠导热结构，从靠近基板的上表面的第一区域的点跨越多个层。 横向导热结构形成在多个层的最上层上方并与第一堆叠导热结构热接触。 本发明有利地有助于散热来自集成电路管芯的热量，特别是从大功率源或其他局部热点消散。

公开(公告)号：US07056819B2

公开(公告)日：2006-06-06

申请号：US10673703

申请日：2003-09-29

Applicant: Sean Lian ,  Vivian Ryan ,  Debra Louise Yencho

Inventor： Sean Lian ,  Vivian Ryan ,  Debra Louise Yencho

IPC: H01L21/44

CPC classification number: H01L24/85 ,  H01L22/12 ,  H01L24/78 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/48 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: Methods and apparatus for performing a wire-bonding operation in an integrated circuit are disclosed. The positions of at least one height-sensing pad and at least one bond pad are determined on a top surface of an integrated circuit die. The height-sensing pad is electrically isolated from the die circuitry and the bond pad is electrically connected to the die circuitry. A bonding tool is lowered to the height-sensing pad, and a height coordinate of the height-sensing pad is then determined. Finally, the bond pad is wire-bonded to a leadframe utilizing the height coordinate of the height-sensing pad.

Abstract translation: 公开了在集成电路中进行引线键合操作的方法和装置。 在集成电路管芯的顶表面上确定至少一个高度感测焊盘和至少一个接合焊盘的位置。 高度感测焊盘与裸片电路电隔离，并且焊盘与裸片电路电连接。 接合工具降低到高度感测垫，然后确定高度感测垫的高度坐标。 最后，使用高度感测垫的高度坐标将接合焊盘引线接合到引线框架上。

公开(公告)号：US20060091480A1

公开(公告)日：2006-05-04

申请号：US10981175

申请日：2004-11-03

Applicant: John Desko ,  Roger Fratti ,  Vivian Ryan

Inventor： John Desko ,  Roger Fratti ,  Vivian Ryan

IPC: H01L23/62

CPC classification number: H01L29/7835 ,  H01L23/4824 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

公开(公告)号：US06207547B1

公开(公告)日：2001-03-27

申请号：US09305766

申请日：1999-05-05

Applicant: Sailesh Chittipeddi ,  Vivian Ryan

Inventor： Sailesh Chittipeddi ,  Vivian Ryan

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

Abstract: The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer. It is believed that the inter-structural cooperation between these two layers provides a graded composite support structure that acts as a differential force transducer to buffer internal and bonding stresses within an integrated circuit.

Abstract translation: 本发明提供一种用于集成电路中的接合焊盘支撑结构，该集成电路具有位于其上的接合焊盘。 在一个实施例中，接合焊盘支撑结构包括位于接合焊盘下方并且具有形成在其中的开口的支撑层。 接合焊盘支撑结构还包括位于导电层上并且至少部分地延伸到开口中以在开口的至少一部分上形成接合焊盘支撑表面的电介质层。 在一个实施例中，第一接合焊盘支撑层可以包括导电金属，并且第二接合焊盘支撑层可以包括电介质材料。 本发明提供了一种独特的接合焊盘结构，其中第一接合焊盘支撑层内的开口至少部分地被第二接合焊盘支撑层填充。 据信这两层之间的结构间协作提供了一种梯度复合支撑结构，其作为差分力传感器来缓冲集成电路内的内部和结合应力。

公开(公告)号：US6087732A

公开(公告)日：2000-07-11

申请号：US162247

申请日：1998-09-28

Applicant: Sailesh Chittipeddi ,  Vivian Ryan

Inventor： Sailesh Chittipeddi ,  Vivian Ryan

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/02 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14

Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

Abstract translation: 接合焊盘支撑结构位于集成电路上的接合焊盘下方。 接合焊盘支撑结构包括至少部分地位于接合焊盘下方的第一接合焊盘支撑层。 第一接合焊盘支撑层具有多个径向图案，其具有在径向图案之间的至少一个空间。 径向图案可以是例如具有近似均匀厚度的直线。 或者，径向图案可以是三角形，每个三角形具有指向接合垫下方的区域的中心的顶点。 径向图案可以具有多个不同的长度。 第二接合焊盘支撑层位于第一接合焊盘支撑层上。 第二接合垫支撑层填充径向图案之间的空间的至少一部分。

公开(公告)号：US08664759B2

公开(公告)日：2014-03-04

申请号：US11158370

申请日：2005-06-22

Applicant: Vivian Ryan

Inventor： Vivian Ryan

IPC: H01L23/34 ,  H01L23/12 ,  H01L23/053 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/20 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract translation: 集成电路管芯包括具有上表面的衬底，形成在衬底的上表面的第一区域中的至少一个有源器件，以及形成在衬底上表面上的至少一个有源器件上的多个层 。 提供了第一层叠导热结构，从靠近基板的上表面的第一区域的点跨越多个层。 横向导热结构形成在多个层的最上层上方并与第一堆叠导热结构热接触。 本发明有利地有助于散热来自集成电路管芯的热量，特别是从大功率源或其他局部热点消散。

公开(公告)号：US07973544B2

公开(公告)日：2011-07-05

申请号：US12194706

申请日：2008-08-20

Applicant: Vance D. Archer, III ,  Daniel P. Chesire ,  Warren K. Gladden ,  Seung H. Kang ,  Taeho Kook ,  Sailesh M. Merchant ,  Vivian Ryan

Inventor： Vance D. Archer, III ,  Daniel P. Chesire ,  Warren K. Gladden ,  Seung H. Kang ,  Taeho Kook ,  Sailesh M. Merchant ,  Vivian Ryan

IPC: G01R31/00

CPC classification number: G01R31/3187 ,  H01L22/34 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention, in one aspect, provides a semiconductor device (100), including transistors (105), dielectric layers (115, 120) located over the transistors (105), interconnects (122) formed within the dielectric layers (115, 120), and a test structure (130) located adjacent a hot-spot (125) of the semiconductor device (100) and configured to monitor a real-time operational parameter of at least one of the transistors (105) or interconnects (122).

Abstract translation: 本发明在一个方面提供了一种半导体器件（100），包括位于晶体管（105）上方的晶体管（105），电介质层（115,120），形成在电介质层（115,120）内的互连（122） 以及位于半导体器件（100）的热点（125）附近并被配置为监视至少一个晶体管（105）或互连（122）的实时操作参数的测试结构（130）。

公开(公告)号：US07745927B2

公开(公告)日：2010-06-29

申请号：US10879909

申请日：2004-06-29

Applicant: Vivian Ryan ,  Richard Handly Shanaman, III

Inventor： Vivian Ryan ,  Richard Handly Shanaman, III

IPC: H01L23/34

CPC classification number: H01L23/3736 ,  H01L23/3735 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/48247 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/05442 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit die includes a substrate having a front surface and a back surface, wherein the substrate front surface has electrical circuits formed thereon, and the substrate back surface has a plurality of metal layers formed thereon. The plurality of metal layers comprises at least one layer having a thickness of greater than about ten micrometers. The outermost metal layer may be mechanically and thermally bonded to a package using a die attach layer comprising a thermally conductive reflowable material. The invention advantageously facilitates the dissipation of heat from the integrated circuit die.

Abstract translation: 集成电路管芯包括具有前表面和后表面的基板，其中基板正面具有形成在其上的电路，并且基板背面上形成有多个金属层。 多个金属层包括至少一层厚度大于约十微米的层。 可以使用包括导热可回流材料的管芯附接层将最外侧的金属层机械地和热结合到封装。 本发明有利地有助于散热来自集成电路管芯的热量。

公开(公告)号：US20080026508A1

公开(公告)日：2008-01-31

申请号：US11868624

申请日：2007-10-08

Applicant: Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

Inventor： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC: H01L21/00

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract translation: 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US20070134903A1

公开(公告)日：2007-06-14

申请号：US11298030

申请日：2005-12-09

Applicant: Vivian Ryan

Inventor： Vivian Ryan

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The metallization layer is in electrical contact with at least a portion of the active circuitry. In addition, the capping layer is formed over at least a portion of the metallization layer and is in electrical contact with the metallization layer. The grooves in the capping layer may be located only proximate to the edges of the bond pad or may run throughout the bond pad depending on the application.

Abstract translation: 集成电路包括有源电路和至少一个接合焊盘。 所述至少一个接合焊盘又包括金属化层和具有一个或多个凹槽的覆盖层。 金属化层与有源电路的至少一部分电接触。 此外，覆盖层形成在金属化层的至少一部分上并且与金属化层电接触。 覆盖层中的凹槽可以仅位于接合焊盘的边缘附近，或者可以根据应用而贯穿焊接垫。