公开(公告)号：US5917229A

公开(公告)日：1999-06-29

申请号：US688241

申请日：1996-07-29

申请人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

发明人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

IPC分类号： G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L29/00

CPC分类号： H05K7/1092 ,  G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  G01R1/06 ,  G01R31/2863 ,  H01L2924/0002 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

摘要： Two types of programmable elements, fuses and antifuses, are disclosed for interconnecting the terminals of electronic components mounted on printed circuit boards (PCBs), multichip modules (MCMs) or in integrated circuit packages (IC packages). Both types of programmable elements can be fabricated as part of the regular processes used to fabricate PCBs, MCMs, or IC package (pin grid array). For fuses and antifuses, the material, geometry and dimensions can be varied to minimize the real estate and maximize programming efficiency (reduce programming time). Each type of programmable element, fuse or antifuse, can be separately used in matrices to form programmable board and package substrates. When both types of programmable elements are used together, more efficient placement and route architectures take advantage of the characteristics of each type of programmable element. Furthermore, combinations of both fuses and antifuses in the same structure allows the architecture to be reprogrammable. Fuse and antifuses can be easily used to form programmable burn-in boards and field programmable smart cards, credit cards, sockets and cable connectors.

摘要翻译： 公开了两种类型的可编程元件，熔丝和反熔丝，用于互连安装在印刷电路板（PCB），多芯片模块（MCM）或集成电路封装（IC封装）中的电子部件的端子。 可以将两种类型的可编程元件制造为用于制造PCB，MCM或IC封装（引脚栅阵列）的常规工艺的一部分。 对于保险丝和反熔丝，可以改变材料，几何形状和尺寸以最小化房地产并最大化编程效率（减少编程时间）。 每种类型的可编程元件，熔丝或反熔丝可以单独用于矩阵中，以形成可编程的板和封装衬底。 当两种类型的可编程元件一起使用时，更有效的布局和布线架构可以利用每种可编程元件的特性。 此外，在相同结构中的熔丝和反熔丝的组合允许架构可重新编程。 保险丝和反熔丝可以轻松地用于形成可编程的老化板和现场可编程智能卡，信用卡，插座和电缆连接器。

公开(公告)号：US5834824A

公开(公告)日：1998-11-10

申请号：US405259

申请日：1995-03-14

申请人： William H. Shepherd ,  Steve S. Chiang ,  John Y. Xie

发明人： William H. Shepherd ,  Steve S. Chiang ,  John Y. Xie

IPC分类号： G01R1/04 ,  G01R1/06 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L27/02

CPC分类号： H05K7/1092 ,  G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5252 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  G01R1/06 ,  H01L2924/0002 ,  H01R23/70 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

摘要： A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called "composite antifuse") has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called "hybrid antifuse") includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.

摘要翻译： 一种新颖的反熔丝包括分散在整个非导电基质中的导电颗粒的复合物，该复合材料位于反熔丝通孔内部。 反熔丝通孔由分离两个电极的电介质层限定。 电极可以位于相同的导电层平面（通常彼此平行并彼此隔离）或两个不同的导电平面（通常形成为彼此横向并由其中形成有反熔丝通孔的电介质隔开）。 电极可以耦合到例如集成电路的有源或无源区域。 反熔丝（也称为“复合反熔丝”）的一个实施例仅在两个导电层之间的反熔丝通孔中具有复合材料。 反熔丝（也称为“混合反熔丝”）的另一实施例除了复合材料之外还包括一个或多个薄介电层，其也位于两个导电层之间的反熔丝中。

公开(公告)号：US5766492A

公开(公告)日：1998-06-16

申请号：US654114

申请日：1996-05-28

申请人： Toshiya Sadahisa ,  Johji Nakamoto ,  Kanji Nishijima ,  Yoshinobu Kurosaki

发明人： Toshiya Sadahisa ,  Johji Nakamoto ,  Kanji Nishijima ,  Yoshinobu Kurosaki

IPC分类号： H01L21/48 ,  H05K3/06 ,  H05K3/24 ,  H05K3/40 ,  B44C1/22

CPC分类号： H01L21/4846 ,  H05K3/242 ,  H05K2203/0542 ,  H05K2203/135 ,  H05K3/064 ,  H05K3/4007

摘要： A method of metal-plating electrode portions of a printed-wiring board includes copper-plating the overall surface of the printed-wiring board on which an electric circuit has been formed, forming a metal plating resist coating on the copper plated wiring board except for on the electrode portions, and subjecting the electrode portions, which are not covered with the resist coating, to an electrolytic metal plating process, at least once, and then removing the remaining resist coating. The resist coating formation and the electrolytic metal plating process may optionally be repeated a predetermined number of times. An etching resist coating is then formed on the circuit portion including the electrode portions, and the copper-plated portion is then removed except from the circuit portion by etching and then stripping the etching resist coating.

摘要翻译： 印刷布线板的金属电镀电极部分的方法包括镀覆印刷电路板的其上形成有电路的整个表面的铜电镀，在镀铜布线板上形成金属电镀保护膜，除了 在电极部分上，并且将未被抗蚀剂涂层覆盖的电极部分进行电解金属电镀处理，至少一次，然后除去剩余的抗蚀剂涂层。 抗蚀剂涂层形成和电解金属电镀工艺可以可选地重复预定次数。 然后在包括电极部分的电路部分上形成抗蚀剂涂层，然后通过蚀刻除去电路部分之外除去镀铜部分，然后剥离抗蚀剂涂层。

公开(公告)号：US5537108A

公开(公告)日：1996-07-16

申请号：US319851

申请日：1994-10-07

申请人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu

发明人： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu

IPC分类号： G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H04Q1/18

CPC分类号： G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

摘要： A programming method in accordance with this invention partitions traces of a fuse matrix into groups wherein each group contains traces connected to fuses that are to remain intact. All of the traces in a group are connected to a first voltage so that the fuses between traces in the group are subjected to minimal currents. In one embodiment, all of the traces that are not in the group connected to the first voltage are connected to a second voltage such that a programming current passes through fuses to be programmed. In an alternative embodiment, traces in a second group are connected to the second voltage and all of the remaining traces are shorted to each other.

摘要翻译： 根据本发明的编程方法将熔丝矩阵的迹线分成组，其中每组包含连接到保持完整的熔丝的迹线。 组中的所有迹线都连接到第一电压，使得组中迹线之间的熔丝经受最小电流。 在一个实施例中，不在连接到第一电压的组中的所有迹线被连接到第二电压，使得编程电流通过待编程的熔丝。 在替代实施例中，第二组中的迹线连接到第二电压，并且所有剩余的迹线彼此短接。

公开(公告)号：US5513430A

公开(公告)日：1996-05-07

申请号：US293365

申请日：1994-08-19

申请人： Arnold W. Yanof ,  William Dauksher

发明人： Arnold W. Yanof ,  William Dauksher

IPC分类号： G01R3/00 ,  H05K3/40 ,  H05K3/02

CPC分类号： H05K3/4007 ,  G01R3/00 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2203/0542 ,  H05K2203/0577 ,  Y10T29/49155

摘要： A probe card (40, 55) having probe card probes (36, 56) and a method for fabricating the probe card probes (36, 56). A layer of resist (23) is formed on a plating base (21). The layer of resist (23) is exposed to radiation (32) and developed to provide angled, tapered openings (33) exposing portions of the plating base (22). An electrically conductive material is electroplated on the exposed portions of the plating base (22) and fills the angled, tapered openings (33). The layer of resist (23) and portions of the plating base (22) between the electroplated conductive material are removed. The electrically conductive material forms the probe card probes (36) which are angled and tapered. In addition, the compliant probe card probes (56) may be stair-step shaped.

摘要翻译： 具有探针卡探针（36,56）的探针卡（40,55）和用于制造探针卡探针（36,56）的方法。 在电镀基体（21）上形成有抗蚀剂层（23）。 抗蚀剂层（23）暴露于辐射（32）并显影以提供倾斜的锥形开口（33），暴露电镀基底（22）的部分。 导电材料电镀在电镀基座（22）的露出部分上并填充有角度的锥形开口（33）。 去除了电镀层（23）和电镀基底（22）在电镀导电材料之间的部分。 导电材料形成了成角度和锥形的探针卡探头（36）。 此外，兼容的探针卡探针（56）可以是台阶形状。

公开(公告)号：US3878007A

公开(公告)日：1975-04-15

申请号：US36754173

申请日：1973-06-06

申请人： RCA CORP

发明人： FELDSTEIN NATHAN ,  LAW HAROLD BELL

IPC分类号： C23C18/16 ,  G03F1/72 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/22 ,  B29C17/08

CPC分类号： G03F1/72 ,  C23C18/1608 ,  C23C18/1689 ,  H05K1/0306 ,  H05K3/062 ,  H05K3/108 ,  H05K3/181 ,  H05K3/225 ,  H05K2201/0344 ,  H05K2203/0542 ,  H05K2203/072

摘要： The method comprises depositing a thin layer of a first metal having a relatively high degree of solubility in a particular etchant on a substrate, this first metal being catalytic to electroless deposition of a second metal to be subsequently deposited, electrolessly depositing on the first metal a pattern of areas of a second metal which has a relatively low degree of solubility in the etchant, and then treating the plated areas with the etchant, so that the first metal is removed where it is not covered by the second metal but the second metal is substantially unaffected.

摘要翻译： 该方法包括在衬底上的特定蚀刻剂中沉积具有较高溶解度的第一金属薄层，该第一金属被催化以无序沉积待随后沉积的第二金属，无电沉积在第一金属a上 在蚀刻剂中具有相对低的溶解度的第二金属的区域图案，然后用蚀刻剂处理镀覆区域，使得第一金属在不被第二金属覆盖的地方被除去，但第二金属是 基本上不受影响。

公开(公告)号：US3457638A

公开(公告)日：1969-07-29

申请号：US3457638D

申请日：1967-02-27

申请人： BRITISH AIRCRAFT CORP LTD

发明人： JOHNSON LEONARD J W

IPC分类号： H05K3/24 ,  H05K3/42 ,  H05K3/06 ,  B41M3/08

CPC分类号： H05K3/428 ,  H05K3/243 ,  H05K3/427 ,  H05K2201/0166 ,  H05K2201/09736 ,  H05K2203/0143 ,  H05K2203/0542 ,  H05K2203/0565 ,  H05K2203/0577 ,  H05K2203/1383 ,  H05K2203/1388 ,  H05K2203/1415 ,  Y10T29/49165

公开(公告)号：US08859420B2

公开(公告)日：2014-10-14

申请号：US13085126

申请日：2011-04-12

申请人： Kimitaka Endo ,  Norihito Masuda ,  Tomokazu Shimada

发明人： Kimitaka Endo ,  Norihito Masuda ,  Tomokazu Shimada

IPC分类号： H01L23/04 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46 ,  H01L21/48 ,  H05K3/20 ,  H05K3/42 ,  H05K3/06

CPC分类号： H05K3/4617 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L2924/0002 ,  H05K3/064 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4647 ,  H05K2203/0384 ,  H05K2203/0542 ,  H05K2203/0733 ,  Y10S438/931 ,  Y10T29/49124 ,  H01L2924/00

摘要： A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.

摘要翻译： 制造互连元件的方法可以包括制造覆盖载体层并且包括多个金属迹线的金属层; 提供介电元件以覆盖金属层和载体层; 提供多个金属柱; 以及去除载体层以暴露介质元件的第一主表面和多个金属迹线的外表面。

公开(公告)号：US20120124830A1

公开(公告)日：2012-05-24

申请号：US13362958

申请日：2012-01-31

申请人： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

发明人： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC分类号： H05K3/10

CPC分类号： H05K3/4007 ,  H05K3/06 ,  H05K3/062 ,  H05K3/107 ,  H05K3/3452 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

摘要翻译： 提供一种制造电路板的工艺。 在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。 接下来，在电路基板上形成阻挡材料层。 阻挡材料层完全覆盖绝缘层和垫。 然后，在阻挡材料层上形成至少一个导电凸块。 导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。 接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

公开(公告)号：US20090304910A1

公开(公告)日：2009-12-10

申请号：US12541407

申请日：2009-08-14

申请人： Masayuki Nagamatsu ,  Ryosuke Usui

发明人： Masayuki Nagamatsu ,  Ryosuke Usui

IPC分类号： H05K3/00 ,  C25D5/02

CPC分类号： H05K1/111 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/383 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/0542 ,  Y02P70/611 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401

摘要： An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region. A solder resist is formed in such a manner as to cover part of the gold plating layer and the wiring pattern corresponding to the boundary region and the wiring region, and the solder resist has a predetermined opening through which to connect to the semiconductor device. A conductive member is connected to the gold plating layer in the electrode region, and a molded resin layer seals the entire semiconductor module.

摘要翻译： 本发明的优点是抑制从焊盘电极部分渗透的湿气在布线图案的表面上扩散，并提高包装板的可靠性。 包装板的布线图案形成在绝缘基板上，并且包括布线区域，与半导体器件连接的电极区域（焊盘电极）以及设置在布线区域和电极区域之间的边界区域。 在布线图案的电极区域的表面上设置镀金层。 布线图案的边界区域的顶表面被形成为从布线图案的布线区域的顶表面凹陷，并且在边界区域中设置有台阶部分。 形成阻焊层，以覆盖与边界区域和布线区域相对应的金镀层和布线图案的一部分，阻焊剂具有与半导体器件连接的预定开口。 导电构件连接到电极区域中的镀金层，并且模制树脂层密封整个半导体模块。