公开(公告)号：US09526179B2

公开(公告)日：2016-12-20

申请号：US14635952

申请日：2015-03-02

Applicant: MUTUAL-TEK INDUSTRIES CO., LTD.

Inventor： Chiu Yu Chen ,  Wen-Chin Lai ,  Pui-Ren Jiang ,  Hsu-Tung Chen

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  H05K3/20

CPC classification number: H05K3/007 ,  H05K3/20 ,  H05K3/4691 ,  H05K2201/09509 ,  Y10T156/1039

Abstract: A printed circuit board and the method of manufacturing the same are provided. The printed circuit board comprises a supporting plate having a front side and a rear side; a first adhesive layer placed on the front side of the supporting plate; and a front wire layer embedded into the first adhesive layer. The front wire layer includes at least one external contact portion for connecting an electronic component, wherein the surface of the external contact portion is coplanar with the surface of the first adhesive layer surrounding the external contact portion.

Abstract translation: 提供一种印刷电路板及其制造方法。 印刷电路板包括具有前侧和后侧的支撑板; 第一粘合剂层，其设置在所述支撑板的前侧; 以及嵌入到第一粘合剂层中的前线层。 前线层包括用于连接电子部件的至少一个外部接触部分，其中外部接触部分的表面与包围外部接触部分的第一粘合剂层的表面共面。

公开(公告)号：US20160366768A1

公开(公告)日：2016-12-15

申请号：US15107931

申请日：2015-02-16

Applicant: NIPPON MEKTRON, LTD.

Inventor： Fumihiko MATSUDA

IPC: H05K3/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K3/025 ,  H05K1/02 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/24 ,  H05K3/40 ,  H05K3/4053 ,  H05K3/4685 ,  H05K2201/0141 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/05 ,  H05K2201/09509 ,  H05K2201/10363 ,  H05K2203/0264 ,  H05K2203/0568

Abstract: The manufacturing method of the flexible printed wiring board relating to an embodiment includes a step of preparing a metal foil clad laminate 1 including an insulating substrate 2 and metal foil 3 and metal foil 4 provided on main surfaces of the substrate 2, a step of forming a circuit pattern 5 by patterning the metal foil 3, a step of forming a peelable printing plate layer 6 on the substrate 2 so as to embed the pattern 5, a step of forming blind holes 7a and 7b where the pattern 5 is exposed inside by partially removing the printing plate layer 6, a step of printing conductive paste with the printing plate layer 6 as a printing mask, and filling the conductive paste 8 inside the blind holes, and a step of peeling off the printing plate layer 6 from the metal foil clad laminate 1.

Abstract translation: 本实施方式的柔性印刷电路板的制造方法包括：准备包括绝缘基板2和金属箔3的金属箔覆层压板1和设置在基板2的主面上的金属箔4的工序， 通过图案化金属箔3的电路图案5，在基板2上形成可剥离印刷版层6以嵌入图案5的步骤，形成盲孔7a和7b的步骤，其中图案5暴露在内部的情况下通过 部分地除去印版层6，印刷印刷层6作为印刷掩模印刷导电浆料的步骤，并将导电浆料8填充在盲孔内部，以及从印刷板6剥离金属的步骤 箔包覆层压板1。

公开(公告)号：US20160336287A1

公开(公告)日：2016-11-17

申请号：US15222873

申请日：2016-07-28

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng LIAO ,  Chia-Ching CHEN ,  Yi-Chuan DING

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

Abstract translation: 半导体封装结构包括衬底，半导体芯片和焊料材料。 基板包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入。 导电电路层包括焊盘，焊盘的侧表面沿绝缘层的侧表面延伸。 导电凸块设置在垫上。 导电凸块的侧表面，焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 焊料材料电连接导电凸块和半导体芯片。 焊接材料的一部分设置在容纳空间中。

公开(公告)号：US09437565B2

公开(公告)日：2016-09-06

申请号：US14586735

申请日：2014-12-30

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

Abstract translation: 本公开涉及包括半导体衬底，半导体芯片和导电材料的半导体封装结构。 半导体衬底包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入，并且包括至少一个焊盘。 导电凸块设置在至少一个垫上。 导电凸块的侧表面，至少一个焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 导电材料与导电凸块和半导体芯片电连接，导电材料的一部分设置在容纳空间中。

公开(公告)号：US20160190079A1

公开(公告)日：2016-06-30

申请号：US14586735

申请日：2014-12-30

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng LIAO ,  Chia-Ching CHEN ,  Yi-Chuan DING

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

Abstract translation: 本公开涉及包括半导体衬底，半导体芯片和导电材料的半导体封装结构。 半导体衬底包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入，并且包括至少一个焊盘。 导电凸块设置在至少一个垫上。 导电凸块的侧表面，至少一个焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 导电材料与导电凸块和半导体芯片电连接，导电材料的一部分设置在容纳空间中。

公开(公告)号：US09338899B2

公开(公告)日：2016-05-10

申请号：US14106013

申请日：2013-12-13

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yang Je Lee ,  Il Woon Shin ,  Going Sik Kim ,  Doo Pyo Hong ,  Ha Il Kim ,  Dong Gi An

IPC: H05K3/20 ,  H05K3/42 ,  H05K1/02 ,  H05K3/00 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K3/429 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4664 ,  H05K3/4691 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2203/054 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: A method of manufacturing a rigid-flexible printed circuit board includes providing a base substrate in which coverlays are respectively formed on two sides of a flexible copper foil laminate on both sides of which inner circuit patterns and a first window are respectively formed; layering insulation layers and copper foil layers on portions of coverlays which are to be a rigid region of the base substrate; forming a via hole in the rigid region, and, simultaneously, forming a via hole to correspond to the first window in a flexible region; forming outer circuit patterns including areas adjacent to the first window; and applying solder resists in the rigid region to expose portions of external circuit patterns. The region adjacent to the via holes in the flexible region includes additional plating portions for covering the coverlays.

Abstract translation: 一种刚性柔性印刷电路板的制造方法，其特征在于，在其两侧分别形成有内层电路图案和第一窗口的柔性铜箔层叠体的两面分别形成有覆盖层的基板， 在作为基底基板的刚性区域的覆盖层的部分上分层绝缘层和铜箔层; 在刚性区域中形成通孔，同时在柔性区域中形成与第一窗口对应的通孔; 形成包括与所述第一窗口相邻的区域的外部电路图案; 并在刚性区域中施加阻焊剂以暴露部分外部电路图案。 与柔性区域中的通孔相邻的区域包括用于覆盖覆盖层的附加电镀部分。

公开(公告)号：US09332638B2

公开(公告)日：2016-05-03

申请号：US14118636

申请日：2012-05-23

Applicant: Kiminori Ozaki ,  Yasuhiro Koike ,  Hiroaki Asano ,  Harumitsu Sato ,  Hiroki Watanabe ,  Tadayoshi Kachi ,  Takahiro Suzuki ,  Hitoshi Shimadu ,  Tetsuya Furuta ,  Masao Miyake ,  Takahiro Hayakawa ,  Tomoaki Asai ,  Ryou Yamauchi

Inventor： Kiminori Ozaki ,  Yasuhiro Koike ,  Hiroaki Asano ,  Harumitsu Sato ,  Hiroki Watanabe ,  Tadayoshi Kachi ,  Takahiro Suzuki ,  Hitoshi Shimadu ,  Tetsuya Furuta ,  Masao Miyake ,  Takahiro Hayakawa ,  Tomoaki Asai ,  Ryou Yamauchi

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K1/02

CPC classification number: H05K1/11 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038 ,  H05K3/4046 ,  H05K3/4084 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2203/033 ,  H05K2203/1178 ,  Y10T29/49165

Abstract: An electrically conductive path is configured from a first copper plate, a second copper plate, and solder. The first copper plate has a first bent section extended from a first joining section joined to an electrically insulative board and bent toward the rear surface of the electrically insulative board. The second copper plate has a second bent section which is extended from a second joining section joined to the electrically insulative board, is bent toward the front surface of the electrically insulative board, and is disposed so as to cover, together with the first bent section, the inner wall surface of a base-material through-hole. Through-holes are provided in the portions of the second copper plate which face the inside of the base-material through-hole. Solder is filled between the first bent section and the second bent section.

Abstract translation: 导电路径由第一铜板，第二铜板和焊料构成。 第一铜板具有从接合到电绝缘板的第一接合部延伸并朝向电绝缘板的后表面弯曲的第一弯曲部。 第二铜板具有从连接到电绝缘板的第二接合部延伸的第二弯曲部，朝向电绝缘板的前表面弯曲，并且与第一弯曲部一起覆盖 ，基材通孔的内壁表面。 在第二铜板的与基材通孔的内侧相对的部分设有通孔。 焊料填充在第一弯曲部分和第二弯曲部分之间。

公开(公告)号：US09321741B2

公开(公告)日：2016-04-26

申请号：US13695508

申请日：2010-04-30

Applicant: Hiroki Yasuda ,  Ryoichi Kimizuka ,  Tatsuji Takasu ,  Takuro Sato ,  Hiroshi Ishizuka ,  Yasuhiro Ogo ,  Yuto Oyama ,  Yu Tonooka ,  Mikiko Kosaka ,  Aya Shimomura ,  Yumiko Shimizu

Inventor： Hiroki Yasuda ,  Ryoichi Kimizuka ,  Tatsuji Takasu ,  Takuro Sato ,  Hiroshi Ishizuka ,  Yasuhiro Ogo ,  Yuto Oyama ,  Yu Tonooka ,  Mikiko Kosaka ,  Aya Shimomura ,  Yumiko Shimizu

IPC: C25D3/38 ,  C07D295/08 ,  C07D295/088 ,  H01L21/768 ,  H01L21/288 ,  H05K3/42 ,  H05K3/46

CPC classification number: C07D295/08 ,  C07D295/088 ,  C25D3/38 ,  H01L21/2885 ,  H01L21/76898 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09563

Abstract: Provided is a copper plating technique that enables the filling of high aspect-ratio via-holes and through-holes in semiconductor substrates such as silicon substrates, organic material substrates or ceramic substrates. The disclosed technique involves a tertiary amine compound, which is obtained by reacting a heterocyclic compound with the epoxy group of a glycidyl ether group of a compound that has three or more glycidyl ether groups, and a quaternary amine compound thereof, as well as a copper plating additive, a copper plating bath, and a copper plating method employing the compounds.

Abstract translation: 提供一种铜电镀技术，其能够填充诸如硅衬底，有机材料衬底或陶瓷衬底的半导体衬底中的高纵横比通孔和通孔。 所公开的技术涉及通过使杂环化合物与具有三个或更多个缩水甘油醚基团的化合物的缩水甘油醚基团的环氧基及其季胺化合物反应而获得的叔胺化合物，以及铜 电镀添加剂，铜电镀浴和使用该化合物的镀铜方法。

公开(公告)号：US20160113114A1

公开(公告)日：2016-04-21

申请号：US14977669

申请日：2015-12-22

Applicant: Unimicron Technology Corp.

Inventor： Ying-Chih Chan ,  Chun-Ting Lin

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K3/4015 ,  H05K3/0097 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/041 ,  H05K2203/1536

Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上，并且具有第三表面，第四表面和暴露第一电路层的第一开口。 导电块填充第一开口并与第一电路层连接。 每个导电块的顶表面高于绝缘层的第三表面。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。

公开(公告)号：US20160037653A1

公开(公告)日：2016-02-04

申请号：US14699808

申请日：2015-04-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dong Hun KANG ,  Joung Suk LEE

IPC: H05K3/42 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/429 ,  H05K1/0225 ,  H05K1/115 ,  H05K3/445 ,  H05K2201/09509 ,  H05K2203/061

Abstract: There are provided an insulating film, a printed circuit board including the insulating film, and a method of manufacturing the printed circuit board. The insulating film includes a first insulating material; a second insulating material; and a metal thin film disposed between the first insulating material and the second insulating material.

Abstract translation: 提供绝缘膜，包括绝缘膜的印刷电路板以及制造印刷电路板的方法。 绝缘膜包括第一绝缘材料; 第二绝缘材料; 以及设置在所述第一绝缘材料和所述第二绝缘材料之间的金属薄膜。