公开(公告)号：US09226435B2

公开(公告)日：2015-12-29

申请号：US14171623

申请日：2014-02-03

Applicant: Apple Inc.

Inventor： Joseph Fisher, Jr. ,  Sean Mayo ,  Dennis R. Pyper ,  Paul Nangeroni ,  Jose Mantovani

IPC: H05K5/00 ,  H05K9/00 ,  H05K3/28 ,  H01L23/552

CPC classification number: H05K9/0084 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15192 ,  H05K3/284 ,  H05K9/0092 ,  H05K2201/0715 ,  H05K2201/09509 ,  H01L2924/00

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.

Abstract translation: 诸如集成电路的电气部件可以安装在印刷电路板上。 为了防止电气部件受到电磁干扰，可以在部件上形成射频屏蔽结构。 射频屏蔽结构可以由一层金属涂料形成。 组件可以被一层电介质覆盖。 可以在电路块之间的电介质中形成通道。 金属涂料可用于涂覆电介质的表面并填充通道。 可以在金属涂料的表面中形成开口以将射频屏蔽彼此分开。 印刷电路板表面上的导电迹线可用于将金属漆层连接到内部印刷电路板迹线。

公开(公告)号：US20150372403A1

公开(公告)日：2015-12-24

申请号：US14311293

申请日：2014-06-21

Applicant: Keysight Technologies, Inc.

Inventor： Kuen Yew Lam ,  Thiam Ping Oon ,  Jared Richard

IPC: H01R12/58 ,  H05K3/46 ,  H05K3/36 ,  H05K3/42 ,  H05K1/18 ,  H05K1/11

CPC classification number: H01R12/585 ,  H05K1/115 ,  H05K1/162 ,  H05K7/1452 ,  H05K2201/044 ,  H05K2201/09509 ,  H05K2201/1059 ,  Y10T29/49128 ,  Y10T29/51 ,  Y10T156/1057

Abstract: An apparatus comprises a printed circuit board (PCB) having a first surface and a second surface, a plurality of blind press-fit vias penetrating the first surface and extending partially through the PCB toward the second surface, the blind press-fit vias configured to receive press-fit connectors of at least one component to be connected to the PCB, and a plurality of electrical connectors disposed in a region of the second surface opposite the blind press-fit vias and configured to interface with one or more signal processing components disposed on the second surface.

Abstract translation: 一种装置包括具有第一表面和第二表面的印刷电路板（PCB），穿过第一表面并且部分地延伸通过PCB朝向第二表面延伸的多个盲压配合通孔，盲压配合通孔被配置为 接收要连接到PCB的至少一个部件的压入连接器;以及多个电连接器，其布置在与所述盲压配合过孔相对的所述第二表面的区域中，并被配置为与设置的一个或多个信号处理部件 在第二个表面。

公开(公告)号：US20150349398A1

公开(公告)日：2015-12-03

申请号：US14825682

申请日：2015-08-13

Applicant: FUJIKURA, LTD.

Inventor： Yusuke UEMICHI

IPC: H01P11/00

CPC classification number: H01P11/003 ,  H01P5/107 ,  H05K1/0251 ,  H05K3/002 ,  H05K3/0029 ,  H05K2201/037 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2203/0733 ,  Y10T29/49018

Abstract: A method for manufacturing a mode converter including a substrate that is a single member and includes a first main surface, a second main surface opposite to the first main surface, and a micro hole which is formed in the first main surface, grounding conductor layers that are formed on the first main surface and the second main surface, a plane circuit that is formed on the first main surface, and a pin that is formed so as to cover an inner surface of the micro hole and is electrically connected to the plane circuit, the method includes: irradiating the substrate with laser light to form a first modified portion to a desired depth from one main surface of the substrate; removing the first modified portion to form the micro hole; and filling the micro hole with a conductive material to form the pin.

Abstract translation: 一种制造模式转换器的方法，该模式转换器包括作为单个部件的基板，包括第一主表面，与第一主表面相对的第二主表面和形成在第一主表面中的微孔，接地导体层， 形成在第一主表面和第二主表面上，形成在第一主表面上的平面电路和形成为覆盖微孔的内表面并且与平面电路电连接的销 所述方法包括：用激光照射所述基板，以从所述基板的一个主表面形成到所需深度的第一改质部分; 去除所述第一改性部分以形成所述微孔; 并用导电材料填充微孔以形成销。

公开(公告)号：US09204546B2

公开(公告)日：2015-12-01

申请号：US14181739

申请日：2014-02-17

Applicant: Chin-Sheng Wang ,  Ching-Sheng Chen ,  Chun-Kai Lin ,  Chao-Min Wang

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Chun-Kai Lin ,  Chao-Min Wang

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00

CPC classification number: H05K1/113 ,  H05K1/115 ,  H05K3/0097 ,  H05K3/4007 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/1536 ,  H05K2203/1563 ,  Y10T29/49165

Abstract: A circuit board includes a circuit layer, a first solder resist layer, a second solder resist layer and at least one conductive bump. The first solder resist layer is disposed on a lower surface of the circuit layer and has at least one first opening exposing a portion of the lower surface of the circuit layer. The second solder resist layer is disposed on an upper surface of the circuit layer and has at least one second opening exposing a portion of the upper surface of the circuit layer. The conductive bump is disposed inside the second opening of the second solder resist layer and directly connects to the upper surface of the circuit layer exposed by the second opening. A top surface of the conductive bump is higher than a second surface of the second solder resist layer.

Abstract translation: 电路板包括电路层，第一阻焊层，第二阻焊层和至少一个导电凸块。 第一阻焊层设置在电路层的下表面上，并且具有暴露电路层的下表面的一部分的至少一个第一开口。 第二阻焊层设置在电路层的上表面上，并且具有暴露电路层的上表面的一部分的至少一个第二开口。 导电凸块设置在第二阻焊层的第二开口内，并且直接连接到由第二开口暴露的电路层的上表面。 导电凸块的顶表面高于第二阻焊层的第二表面。

公开(公告)号：US20150319863A1

公开(公告)日：2015-11-05

申请号：US14700438

申请日：2015-04-30

Applicant: Dhananjaya Turpuseema ,  Thomas P. Warwick ,  Thomas Smith ,  James V. Russell

Inventor： Dhananjaya Turpuseema ,  Thomas P. Warwick ,  Thomas Smith ,  James V. Russell

IPC: H05K1/18 ,  H05K3/36 ,  H05K3/46 ,  H05K3/32 ,  H05K1/14 ,  H05K3/00

CPC classification number: H05K1/188 ,  H05K1/144 ,  H05K1/183 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/0094 ,  H05K3/321 ,  H05K3/366 ,  H05K3/4655 ,  H05K3/4679 ,  H05K2201/032 ,  H05K2201/0355 ,  H05K2201/042 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2203/0485 ,  H05K2203/063 ,  H05K2203/11 ,  Y10T29/49128 ,  Y10T29/4914

Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component. This structure also uses a permanent and highly conductive attach material to electrically connect the component terminal to the plated side-wall and in a final embodiment the terminals are connected through a conductive attach material through a via in the z axis to a conductive pad.

Abstract translation: 印刷电路板内部的方法和电互连结构，用于在嵌入式组件端子，信号迹线和/或电源/接地平面之间建立可靠的，高性能的连接方法，其可能占据与嵌入式组件相同的垂直空间，例如 作为电容器或电阻器。 通过所述嵌入式组件结构的制造过程进一步减轻组装和可靠性。 在一种结构化的钻孔中，电镀通孔使用永久且高度导电的附着材料将印刷电路板中的迹线或平面连接到嵌入式部件的电气端子。 在另一种结构中，迹线或平面通过选择性侧壁电镀连接，该电镀围绕部件的电端子。 该结构还使用永久且高度导电的附着材料将组件端子电连接到电镀侧壁，并且在最终实施例中，端子通过导电附着材料通过z轴上的通孔连接到导电焊盘。

公开(公告)号：US09107324B2

公开(公告)日：2015-08-11

申请号：US14231758

申请日：2014-04-01

Applicant: Petteri Palm ,  Risto Tuominen ,  Antti Iihola

Inventor： Petteri Palm ,  Risto Tuominen ,  Antti Iihola

IPC: H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/30

CPC classification number: H05K1/09 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H05K1/182 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.

Abstract translation: 制造方法和电路模块，其包括绝缘体层，并且在绝缘体层的内部至少一个部件，其包括其材料包含第一金属的接触区域。 绝缘体层的表面是包括至少第一层和第二层的导体，至少第二层含有第二金属。 电路模块包括接触区域和用于形成电触点的导体之间的接触元件。 接触元件在其接触区域的材料的表面上包括含有第三金属的中间层，使得第一，第二和第三金属是不同的金属和触点 中间层和接触面之间的表面积（ACONT 1）小于接触面积的表面积（APAD）。

公开(公告)号：US09098646B2

公开(公告)日：2015-08-04

申请号：US11837181

申请日：2007-08-10

Applicant: Mumtaz Y. Bora ,  Ronald T. Mora

Inventor： Mumtaz Y. Bora ,  Ronald T. Mora

IPC: H05K1/11 ,  G06F17/50 ,  H05K3/00 ,  H05K3/46

CPC classification number: G06F17/50 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A printed circuit board (PCB) design system and method allows for PCB layouts that can be manufactured using a PCB manufacturing technology selected from multiple PCB manufacturing technologies with minimal or no modification to the PCB layout. In accordance with the exemplary embodiment, the PCB layout is designed to meet all design rules of a High Density Interconnect (HDI) manufacturing technology while minimizing requirements for layout changes when the PCB is manufactured using an Interstitial Via Hole (IVH) manufacturing technology. An IVH PCB includes a plurality of vias positioned within reserved via areas that form connections between at least some conductive elements on the board layers. The conductive elements and the plurality of vias form a layout such that a majority of reserved via areas, of all of the reserved via areas on the printed circuit board, are adequate to accommodate mechanically drilled vias manufactured with the HDI manufacturing technology.

Abstract translation: 印刷电路板（PCB）设计系统和方法允许使用从多个PCB制造技术中选择的PCB制造技术制造的PCB布局，对PCB布局进行最小化或不改变。 根据示例性实施例，PCB布局被设计成满足高密度互连（HDI）制造技术的所有设计规则，同时在使用间隙通孔（IVH）制造技术制造PCB时最小化对布局变化的要求。 IVH PCB包括多个通孔，其定位在保留的通孔区域内，所述通孔区域在板层上的至少一些导电元件之间形成连接。 导电元件和多个通孔形成布局，使得印刷电路板上的所有预留通孔区域中的大部分预留通孔区域足以容纳用HDI制造技术制造的机械钻孔。

公开(公告)号：US09089046B2

公开(公告)日：2015-07-21

申请号：US13747979

申请日：2013-01-23

Applicant: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD. ,  UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD.

Inventor： Jen-Chun Chen ,  Pai-Sheng Shih ,  Hsin-Chin Chang

IPC: H05K1/18 ,  H05K9/00 ,  H05K3/10 ,  H05K1/02 ,  H05K3/28 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16 ,  H01L23/00

CPC classification number: H05K9/002 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/562 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/107 ,  H05K3/284 ,  H05K9/0037 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2201/09509 ,  H05K2203/1316

Abstract: An electronic module includes a circuit board, a plurality of electronic components, a plurality of molding layers, at least one first conductive layer, at least one insulating filler, and one second conductive layer. The circuit board has a first plane and at least one grounding pad on the first plane. The electronic components are mounted on the first plane and electrically connected with the circuit board. The molding layers cover the electronic components and the first plane. The trench appears between two adjacent molding layers. The grounding pad is positioned at the bottom of the trench. The first conductive layer covers the sidewall of the trench and the grounding pad. The grounding pad electrically connected with the first conductive layer. The insulating filler is positioned in the trench. The second conductive layer covers the molding layers and the insulating filler, and electrically connects with the first conductive layer.

Abstract translation: 电子模块包括电路板，多个电子部件，多个成型层，至少一个第一导电层，至少一个绝缘填料和一个第二导电层。 电路板具有第一平面和在第一平面上的至少一个接地垫。 电子部件安装在第一平面上并与电路板电连接。 成型层覆盖电子部件和第一平面。 沟槽出现在两个相邻的成型层之间。 接地垫位于沟槽的底部。 第一导电层覆盖沟槽的侧壁和接地垫。 接地垫与第一导电层电连接。 绝缘填料位于沟槽中。 第二导电层覆盖模制层和绝缘填料，并与第一导电层电连接。

公开(公告)号：US09084379B2

公开(公告)日：2015-07-14

申请号：US13423578

申请日：2012-03-19

Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

IPC: H01K3/10 ,  H05K3/00 ,  H05K3/36 ,  H05K1/00 ,  H05K1/14 ,  H05K3/42 ,  H05K3/20

CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

公开(公告)号：US20150146393A1

公开(公告)日：2015-05-28

申请号：US14337196

申请日：2014-07-21

Applicant: INVENSAS CORPORATION

Inventor： CYPRIAN EMEKA UZOH ,  CHARLES G. WOYCHIK ,  TERRENCE CASKEY ,  BELGACEM HABA ,  HIROAKI SATO ,  PHILIP DAMBERG

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/03 ,  H01L23/498

CPC classification number: H05K1/115 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K2201/0141 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/1105 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Abstract translation: 组件包括具有第一和第二间隔开并平行表面的支撑结构以及沿第一和第二表面之间的方向延伸的多个导电元件。 每个导电元件包含选自铜，铝，镍和铬的布线金属的合金和选自由镓，锗，铟，硒，锡，硫，银，磷和 铋。 该合金具有随导电元件的至少一个方向上的距离而变化的组成。 添加剂的浓度小于或等于导电元件的总原子质量的5％，并且导电元件的电阻率在2.5至30微欧姆厘米之间。