公开(公告)号：US20060114144A1

公开(公告)日：2006-06-01

申请号：US11224432

申请日：2005-09-12

Applicant: Colin Lyden ,  John O'Donnell ,  David Nairn

Inventor： Colin Lyden ,  John O'Donnell ,  David Nairn

IPC: H03M1/38

CPC classification number: H03M1/0641 ,  H03M1/069 ,  H03M1/167 ,  H03M3/424

Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract translation: 本发明涉及用于减少管线模数转换器（ADC）中的积分非线性误差的方法和系统。 本发明在第一实施例中提供了一种方法，包括以下步骤：将模拟抖动信号添加到流水线模数转换器的模拟输入信号，并通过管线将模拟输入信号转换为数字输出信号模拟到 数字转换器 模拟抖动信号的幅度由模数转换器的架构决定。 本发明还在第二实施例中提供一种包括用于将模拟输入信号转换为数字输出信号的流水线模数转换器和耦合到转换器的反馈电路的电路，使得数字输出信号适于具有平均非线性度 误差值约零LSB。

公开(公告)号：US20050185475A1

公开(公告)日：2005-08-25

申请号：US11038242

申请日：2005-01-21

Applicant: John O'Connell ,  Colin Lyden

Inventor： John O'Connell ,  Colin Lyden

IPC: G11C5/00 ,  H03M3/02

CPC classification number: H03M3/368 ,  H03M3/464

Abstract: A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, −1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to −1 or from −1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.

Abstract translation: DAC（1）具有取决于所需的模拟电压电平（Vref 1，Vref 2）的开关（6，S 1 / S 2）向其输送电荷的开关元件电容器（7，Cr）。 输出开关（S 3）闭合，接地开关（S 4）打开，根据接收到的双电平数字输入（+1，-1）将电荷输送到输出端。 如果存在从+1到-1或从-1到+1的输入数字转换，则控制块（2）具有存储器并且确定不活动的输出电平。 对于无效级别，S 3保持打开，并且S 4保持关闭。 因此，对于具有这些转换之一的每个时钟周期，不存在电荷转移，因此没有热噪声。 因此整体噪音大大降低。

公开(公告)号：US20050024106A1

公开(公告)日：2005-02-03

申请号：US10874641

申请日：2004-06-23

Applicant: Michael Keaveney ,  Colin Lyden ,  Patrick Walsh

Inventor： Michael Keaveney ,  Colin Lyden ,  Patrick Walsh

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

公开(公告)号：US06556086B2

公开(公告)日：2003-04-29

申请号：US09957042

申请日：2001-09-20

Applicant: Michael F. Keaveney ,  Colin Lyden

Inventor： Michael F. Keaveney ,  Colin Lyden

IPC: H03L700

CPC classification number: H03L7/1976 ,  G06F7/68

Abstract: A fractional-N synthesizer and method of phase synchronizing the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronization pulse at integer multiples of periods of the input reference signal and gating the synchronization pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.

Abstract translation: 一种分数N合成器和方法，其通过在输入参考信号的周期的整数倍产生同步脉冲并选通同步脉冲以重新初始化内插器，使输出信号与分数N合成器中的输入参考信号相位同步 在分数N合成器中，使输出信号的相位与输入参考信号同步。

公开(公告)号：US6107947A

公开(公告)日：2000-08-22

申请号：US962871

申请日：1997-11-03

Applicant: Colin Lyden

Inventor： Colin Lyden

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/466 ,  H03M3/43 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454

Abstract: In a Sigma Delta converter, a succession of input signal samples are processed in an iterative manner to provide a succession of output signals and feedback signals, which are matched to the input signal samples over a specified frequency range. Two or more successive iterations are carried out in parallel so as to provide a sequence of independent outputs available in parallel. This provision of parallel outputs facilitates an overall increase in the speed of operation of the converter, which is otherwise limited by the maximum available rate of clocking of the converter's filters.

Abstract translation: 在Sigma Delta转换器中，以迭代方式处理一系列输入信号采样，以提供一系列与特定频率范围内的输入信号样本匹配的输出信号和反馈信号。 并行执行两个或多个连续的迭代，以便提供并行可用的独立输出序列。 并行输出的这种提供有助于总体上提高转换器的运行速度，否则转换器滤波器的最大可用时钟速率受到限制。

公开(公告)号：US5189419A

公开(公告)日：1993-02-23

申请号：US702337

申请日：1991-05-20

Applicant: Colin Lyden

Inventor： Colin Lyden

IPC: H03M3/02

CPC classification number: H03M3/35 ,  H03M3/43 ,  H03M3/454

Abstract: A sigma-delta analog to digital converter 1 is disclosed. The digital filter comprises digital integrators (8, 10) for reception of the negative feedback signal of the analog modulator. The digital integrators (8, 10) are connected to replicate processing of the feedback signal by the analog integrators (3, 5). Accordingly, the digital filter and the analog modulator may be reset simultaneously so that there is no time lag between conversion cycles. Thus, single shot operation is achieved.

公开(公告)号：US09389275B2

公开(公告)日：2016-07-12

申请号：US13362208

申请日：2012-01-31

Applicant: Gabriel Banarie ,  Andreas Callanan ,  Damien McCartney ,  Colin Lyden

Inventor： Gabriel Banarie ,  Andreas Callanan ,  Damien McCartney ,  Colin Lyden

IPC: G01R35/00 ,  G01R31/319

CPC classification number: G01R31/3191

Abstract: Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.

Abstract translation: 与测量操作一起提供测量系统校准的技术。 这些技术可以包括在测量系统内的信号处理链中提供参考装置。 激励信号可以通过参考装置驱动，同时其可以连接到测量系统内的信号处理链，并且可以捕获校准响应。 在测量操作期间，参考设备连接可以与信号处理链中的传感器连接互补，激励信号可以通过信号处理链驱动。 可以从系统捕获测量响应。 测量系统可以产生校准的测量信号，其根据校准响应和测量响应考虑系统内的相位和/或幅度误差。

公开(公告)号：US20120162947A1

公开(公告)日：2012-06-28

申请号：US12975847

申请日：2010-12-22

Applicant: Alan O'DONNELL ,  Santiago IRIARTE ,  Mark J. MURPHY ,  Colin LYDEN ,  Gary CASEY ,  Eoin Edward ENGLISH

Inventor： Alan O'DONNELL ,  Santiago IRIARTE ,  Mark J. MURPHY ,  Colin LYDEN ,  Gary CASEY ,  Eoin Edward ENGLISH

IPC: H05K7/00 ,  H01L31/12 ,  H01L29/86 ,  H01L29/8605 ,  H01L23/525 ,  H01L29/92

CPC classification number: G01N27/226 ,  B81B7/00 ,  B81B7/007 ,  B81B2201/0214 ,  G01N27/26 ,  G01N27/4148 ,  H01F17/00 ,  H01F17/04 ,  H01L21/82 ,  H01L23/3677 ,  H01L23/38 ,  H01L23/473 ,  H01L23/481 ,  H01L23/58 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/94 ,  H01L25/16 ,  H01L25/167 ,  H01L27/0694 ,  H01L27/14 ,  H01L27/15 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L28/82 ,  H01L28/86 ,  H01L28/90 ,  H01L31/0392 ,  H01L31/0525 ,  H01L31/0547 ,  H01L31/056 ,  H01L31/06 ,  H01L35/00 ,  H01L35/28 ,  H01L35/30 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H02S10/10 ,  H02S40/38 ,  Y02E10/50 ,  Y02E10/52 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05552 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract translation: 本发明的实施例提供一种集成电路系统，其包括在半导体管芯的前侧制造的第一有源层和在半导体管芯的背面上的第二预制层，并且其中包含电气部件，其中电气部件 包括至少一个分立的无源部件。 集成电路系统还包括耦合第一有源层和第二预制层的至少一个电路径。

公开(公告)号：US20110215957A1

公开(公告)日：2011-09-08

申请号：US12717448

申请日：2010-03-04

Applicant: Derek HUMMERSTON ,  Christopher Peter Hurrell ,  Colin Lyden

Inventor： Derek HUMMERSTON ,  Christopher Peter Hurrell ,  Colin Lyden

IPC: H03M1/12

CPC classification number: H03M1/12

Abstract: A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

Abstract translation: 一种管线模数转换器，包括：第一模数转换器，用于确定模数转换结果的第一部分，以及用于形成残留信号; 用于放大残留信号的放大器，所述放大器包括用于对放大器的偏移进行采样的至少一个偏移采样电容器，其中至少一个电阻与所述至少一个电容器相关联以形成滤波器，并且所述至少一个 电阻器是可变的，使得在偏移的采样期间，可以在第一带宽和小于第一带宽的第二带宽之间切换放大器带宽。

公开(公告)号：US20060208935A1

公开(公告)日：2006-09-21

申请号：US11273220

申请日：2005-11-14

Applicant: Christopher Hurrell ,  Colin Lyden

Inventor： Christopher Hurrell ,  Colin Lyden

IPC: H03M1/12

CPC classification number: H03M1/145 ,  H03M1/144 ,  H03M1/468

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitised; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

Abstract translation: 一种模数转换器，包括：用于接收要被数字化的输入信号的输入; 用于执行模数转换的第一部分并用于输出第一数字结果的第一转换器核心; 第一残差计算器，用于计算第一残差作为输入信号和第一数字结果之间的差; 第二转换器核，用于通过转换第一残差来执行模数转换的第二部分; 其中所述第一和第二转换器核心中的至少一个包括至少三个模数转换引擎和用于控制引擎的操作的控制器，使得引擎协同执行逐次逼近搜索，并且其中多个位可以是 在逐次逼近搜索的单个试验步骤中确定。