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    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
    38.
    发明授权
    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners 有权
    具有裂纹停止区域的半导体芯片，用于减少从芯片边缘/角落的裂纹扩展

    公开(公告)号：US07875502B2

    公开(公告)日：2011-01-25

    申请号：US12788521

    申请日：2010-05-27

    Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC: H01L21/78

    CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

    Abstract translation: 芯片制造方法。 提供的结构包括：半导体衬底上的晶体管，半导体衬底上的N个互连层和晶体管（N> 0），以及N个互连层上的第一介电层。 晶体管电耦合到N个互连层。 在第一介电层（P，Q> 0）上形成有P断裂区域和Q裂纹停止区域。 第一电介质层夹在N互连层和形成在第一介电层上的第二电介质层之间。 每个P裂纹停止区域被第一和第二介电层完全包围。 第二电介质层夹在第一电介质层和形成在第二电介质层上的底部填充层之间。 每个Q裂纹停止区域被第一介电层和底部填充层完全包围。

    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
    39.
    发明申请
    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS 有权
    带切割停止区域的半导体焊盘，用于减少芯片边缘/角落的裂纹传播

    公开(公告)号：US20100233872A1

    公开(公告)日：2010-09-16

    申请号：US12788521

    申请日：2010-05-27

    Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC: H01L21/71

    CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

    Abstract translation: 芯片制造方法。 提供的结构包括：半导体衬底上的晶体管，半导体衬底上的N个互连层和晶体管（N> 0），以及N个互连层上的第一介电层。 晶体管电耦合到N个互连层。 在第一介电层（P，Q> 0）上形成有P断裂区域和Q裂纹停止区域。 第一电介质层夹在N互连层和形成在第一介电层上的第二电介质层之间。 每个P裂纹停止区域被第一和第二介电层完全包围。 第二电介质层夹在第一电介质层和形成在第二电介质层上的底部填充层之间。 每个Q裂纹停止区域被第一介电层和底部填充层完全包围。

    SEMICONDUCTOR CHIP SHAPE ALTERATION
    40.
    发明申请
    SEMICONDUCTOR CHIP SHAPE ALTERATION 审中-公开
    半导体芯片形状改变

    公开(公告)号：US20100019354A1

    公开(公告)日：2010-01-28

    申请号：US12573364

    申请日：2009-10-05

    Applicant: Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

    Inventor： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

    IPC: H01L23/58 ,  H01L23/544

    CPC classification number: H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

    Abstract translation: 本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。 半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。 一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

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