公开(公告)号：US20110175210A1

公开(公告)日：2011-07-21

申请号：US12769053

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552 ,  H01L21/78

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/78 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

摘要翻译： EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片， 在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。 进一步提供通过两个切割工艺的上述结构的制造方法。 第一切割工艺通过切割密封剂形成凹槽。 在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

公开(公告)号：US07804173B2

公开(公告)日：2010-09-28

申请号：US12005764

申请日：2007-12-27

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/14104 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

摘要翻译： 提供了具有导电凸块的半导体器件及其制造方法。 该制造方法主要包括以下步骤：提供具有焊料焊盘和形成在其上的钝化层的半导体衬底，其中一部分焊料焊盘从钝化层暴露出来; 在焊料焊盘上设置第一金属层和围绕焊盘的钝化层的一部分; 在所述第一金属层和所述钝化层上设置覆盖层，以及在所述覆盖层中形成孔以暴露所述第一金属层的一部分，其中所述孔的中心偏离所述焊盘的中心; 在所述第一金属层的所述部分上沉积金属柱; 并在金属柱的外表面上沉积焊料，以提供更好的缓冲效果。

公开(公告)号：US06309914B1

公开(公告)日：2001-10-30

申请号：US09285629

申请日：1999-04-03

申请人： Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L2144

CPC分类号： H01L21/565 ,  H01L24/45 ,  H01L24/97 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a semiconductor package is provided for removing from the semiconductor package excess encapsulant formed by molding compound solidified in the runners and gates of a mold after transfer molding is completed without damaging the semiconductor package. A separator is used to be mounted on a BGA substrate of the semiconductor package for the excess encapsulant to attach thereon, so that the substrate requires no cleaning treatment after transfer molding is completed. In the method, the semiconductor chip is firstly adhered to and electrically connects with the substrate. The substrate with the semiconductor chip is then mounted with the separator having at least one opening for receiving the semiconductor chip, thereby the runners and gates of the mold are positioned over the separator instead of the substrate during transfer molding, allowing the excess encapsulant to attach to the separator. The presence of the separator thus eliminates damages to the substrate caused by the removal of excess encapsulant from the separator and reduces the manufacturing cost of the semiconductor chip for that the separator is capable of repetitive use.

摘要翻译： 提供一种制造半导体封装的方法，用于从半导体封装中去除在传输模制完成之后，通过模塑固化在模具中的浇口和模具中的复合材料形成的多余的密封剂，而不损坏半导体封装。 分离器被用于安装在半导体封装的BGA衬底上，用于使多余的密封剂附着在其上，使得在传送模制完成之后，衬底不需要清洁处理。 在该方法中，首先将半导体芯片粘附并与基板电连接。 然后，具有半导体芯片的基板安装有具有至少一个用于接收半导体芯片的开口的隔板，由此在传送模塑期间模具的浇道和浇口位于隔板上而不是基板上，允许多余的密封剂附着 到分离器。 因此，分离器的存在消除了由分离器去除多余的密封剂而导致的对基板的损坏，并降低了半导体芯片的制造成本，因为隔板能够重复使用。

公开(公告)号：US09040361B2

公开(公告)日：2015-05-26

申请号：US12959148

申请日：2010-12-02

申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Hsin-Yi Liao ,  Hsi-Chang Hsu

发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Hsin-Yi Liao ,  Hsi-Chang Hsu

IPC分类号： H01L23/31 ,  H01L21/58 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L24/82 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/24225 ,  H01L2224/25171 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511

摘要： A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.

摘要翻译： CSP包括：具有带导电焊盘的第一布线层的硬板; 布置在所述导电垫的至少一部分上的多个导电元件; 电子元件具有相反的有源和无效表面，并且经由非活性表面安装在硬板上; 设置在所述硬板上用于封装所述导电元件和电子部件的封装层，所述电子部件的所述有源表面和所述导电元件的表面通过所述封装层露出; 设置在所述封装层上的第一电介质层和第三布线层，所述第三布线层电连接到所述导电元件和所述电子部件，并且还通过所述导电元件与所述第一布线层电连接，从而获得堆叠连接结构 不需要PTH和使用硬板作为主要结构，以避免翘曲。

公开(公告)号：US08975734B2

公开(公告)日：2015-03-10

申请号：US12967839

申请日：2010-12-14

申请人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/81395 ,  H01L2224/81439 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/85001 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

摘要翻译： 其上形成有芯片载体的半导体封装及其制造方法。 金属载体被半蚀刻以形成对应于凹槽的多个凹槽和金属螺柱。 凹槽填充有第一密封剂，并且在金属螺柱上形成多个接合焊盘。 第一密封剂直接与金属螺栓结合。 每个接合焊盘和对应于接合焊盘的一个金属螺柱形成T形结构。 因此，金属螺柱和第一密封剂之间的结合力增强，从而避免分层。 随后进行模具安装，引线接合和成型工艺。 由于半蚀刻槽被第一密封剂填充，因此克服了使现有技术中遇到的导致难以进行运输的柔韧金属载体的缺陷，并且通过不需要使用昂贵的金属来促进制造成本 抗蚀剂层。

公开(公告)号：US08736030B2

公开(公告)日：2014-05-27

申请号：US12769024

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

摘要翻译： 提出了一种具有电磁干扰（EMI）屏蔽功能的四边形扁平非引线（QFN）封装结构，包括：具有管芯焊盘的引线框架，连接到管芯焊盘的多个支撑部分和围绕 裸片焊盘的周边不连接到管芯焊盘; 安装在芯片焊盘上的芯片; 电连接芯片和引线的接合线; 用于封装芯片，接合线和引线框架并暴露引线的侧表面和底表面以及管芯焊盘的底表面的密封剂; 以及屏蔽膜，其设置在密封剂的顶表面和侧表面上，并且电连接到用于屏蔽EMI的支撑部分。 进一步提出如上所述的制造封装结构的方法。

公开(公告)号：US08525348B2

公开(公告)日：2013-09-03

申请号：US12971797

申请日：2010-12-17

申请人： Chiang-Cheng Chang ,  Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chiang-Cheng Chang ,  Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16221 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/19 ,  H01L2224/11

摘要： A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.

摘要翻译： 芯片级封装的制造方法包括提供电子元件，每个电子元件具有带有电极焊盘的活动表面和相对的无效表面，以及设置有软层的硬板; 通过其无效表面将电子部件粘附到软层; 按压电子部件，使得软层在暴露其活性表面的同时封装电子部件; 在电子部件和软质层的有源面上形成介电层; 并且在电介质层上形成第一布线层并与电极焊盘电连接，从而解决了直接将芯片附着在粘合膜上的常规问题，例如膜软化，密封剂溢出，翘曲，芯片偏移和污染 导致在随后的RDL工艺中形成的电极焊盘和布线层之间的电连接不良甚至废物。

公开(公告)号：US20120061825A1

公开(公告)日：2012-03-15

申请号：US12906501

申请日：2010-10-18

申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/82001 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/18162

摘要： A chip scale package and a method of fabricating the chip scale package. The chip scale package includes a encapsulant having a first surface and a second surface opposing the first surface; a conductive pillar formed in the encapsulant and exposed from the first surface and the second surface; a chip embedded in the encapsulant while exposed from the first surface; a dielectric layer formed on the first surface, the conductive pillar and the chip; a circuit layer formed on the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer electrically connecting the circuit layer, electrode pads and the conductive pillar; and a solder mask layer formed on the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure.

摘要翻译： 一种芯片级封装和一种制造芯片级封装的方法。 芯片级封装包括具有第一表面和与第一表面相对的第二表面的密封剂; 形成在所述密封剂中并从所述第一表面和所述第二表面露出的导电柱; 在从第一表面暴露的同时嵌入密封剂中的芯片; 形成在所述第一表面上的电介质层，所述导电柱和所述芯片; 形成在电介质层上的电路层; 形成在电连接电路层，电极焊盘和导电柱的电介质层中的多个导电盲孔; 以及形成在电介质层和电路层上的焊料掩模层，从而根据需要使用导电柱来与其他电子器件外部连接以形成堆叠结构。

公开(公告)号：US20120032347A1

公开(公告)日：2012-02-09

申请号：US12971797

申请日：2010-12-17

申请人： Chiang-Cheng Chang ,  Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chiang-Cheng Chang ,  Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L25/07 ,  H01L23/48 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16221 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/19 ,  H01L2224/11

摘要： A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.

摘要翻译： 芯片级封装的制造方法包括提供电子元件，每个电子元件具有带有电极焊盘的活动表面和相对的无效表面，以及设置有软层的硬板; 通过其无效表面将电子部件粘附到软层; 按压电子部件，使得软层在暴露其活性表面的同时封装电子部件; 在电子部件和软质层的有源面上形成介电层; 并且在电介质层上形成第一布线层并与电极焊盘电连接，从而解决了直接将芯片粘附在粘合膜上的常规问题，例如膜软化，密封剂溢出，翘曲，芯片偏离和污染 导致在随后的RDL工艺中形成的电极焊盘和布线层之间的电连接不良甚至废物。

公开(公告)号：US07934313B1

公开(公告)日：2011-05-03

申请号：US12759237

申请日：2010-04-13

申请人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H05K3/30

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a package structure includes: preparing a metal plate having first and second surfaces and defined with an active region; forming a wiring layer with conductive traces and first electrical contact pads on the first surface; forming third electrical contact pads corresponding to the first electrical contact pads on the second surface; forming a first encapsulant on the first surface; forming on the second surface an open area to penetrate the metal plate, wherein the metal plate form conductive posts between the first and third electrical contact pads; mounting in the open area a chip electrically connected to the wiring layer; forming a second encapsulant in the open area, the wiring layer and the third electrical contact pads; forming first and second openings in the first and second encapsulants to expose the third electrical contact pads, respectively; and cutting the metal plate to remove the metal layer.

摘要翻译： 包装结构的制造方法包括：制备具有第一表面和第二表面并且限定有活性区域的金属板; 在所述第一表面上形成具有导电迹线和第一电接触焊盘的布线层; 形成对应于第二表面上的第一电接触焊盘的第三电接触焊盘; 在所述第一表面上形成第一密封剂; 在所述第二表面上形成穿透所述金属板的开放区域，其中所述金属板在所述第一和第三电接触焊盘之间形成导电柱; 在所述开放区域中安装与所述布线层电连接的芯片; 在所述开放区域中形成第二密封剂，所述布线层和所述第三电接触焊盘; 在第一和第二密封剂中形成第一和第二开口以分别露出第三电接触垫; 并切割金属板以去除金属层。