公开(公告)号：US20110166141A1

公开(公告)日：2011-07-07

申请号：US12960805

申请日：2010-12-06

Applicant: Chun-Cheng Lin ,  Wun-Shaing Wayne Chang ,  Biing-Jiun Uang ,  Jang-Yang Chang ,  Jo-Chun Chen ,  Hsing-Pang Hsieh

Inventor： Chun-Cheng Lin ,  Wun-Shaing Wayne Chang ,  Biing-Jiun Uang ,  Jang-Yang Chang ,  Jo-Chun Chen ,  Hsing-Pang Hsieh

IPC: A61K31/5375 ,  C07C69/66 ,  A61K31/235 ,  C07D241/10 ,  A61K31/4965 ,  C07D295/18 ,  A61P35/00

CPC classification number: C07C261/04 ,  C07C237/22 ,  C07C2601/02 ,  C07C2601/04 ,  C07C2601/14 ,  C07C2601/18 ,  C07C2603/18 ,  C07D209/42 ,  C07D217/26 ,  C07D241/24 ,  C07D249/18 ,  C07D295/215 ,  C07D307/68 ,  C07D309/32 ,  C07D319/18 ,  C07D333/24

Abstract: Cathepsin S inhibitors having formula (I), (II), (III) or (IV) as shown in the specification. These inhibitors can be used to treat cancer and autoimmune/inflammatory diseases.

Abstract translation: 具有式（I），（II），（III）或（IV）的组织蛋白酶S抑制剂，如说明书所示。 这些抑制剂可用于治疗癌症和自身免疫/炎性疾病。

公开(公告)号：USD569179S1

公开(公告)日：2008-05-20

申请号：US29250337

申请日：2006-11-10

Applicant: Chun-Cheng Lin

Designer： Chun-Cheng Lin

公开(公告)号：US07135183B1

公开(公告)日：2006-11-14

申请号：US10213257

申请日：2002-08-06

Applicant: Yuan-Yuan Wang ,  Kay-Hooi Khoo ,  Shui-Tein Chen ,  Chun-Cheng Lin ,  Chi-Huey Wong ,  Chun-Hung Lin ,  Hong-Sen Chen ,  Yow-Fu Tsai

Inventor： Yuan-Yuan Wang ,  Kay-Hooi Khoo ,  Shui-Tein Chen ,  Chun-Cheng Lin ,  Chi-Huey Wong ,  Chun-Hung Lin ,  Hong-Sen Chen ,  Yow-Fu Tsai

IPC: A01N65/00 ,  A61K9/00 ,  A61K47/00 ,  A23K1/17

CPC classification number: A61K36/074 ,  A23L33/105

Abstract: The present invention provides medicinally active extracts and fractions, and a method for preparing the same by extracting and fractioning constituents from the tissue of plant components of Ganoderma lucidum. These active extracts and fractions are useful for inhibiting tumor growth, modulating immune response, and increasing hematopoietic activity.

Abstract translation: 本发明提供了药用活性提取物和级分，以及通过从灵芝植物组分的组织提取和分馏成分的方法及其制备方法。 这些活性提取物和级分可用于抑制肿瘤生长，调节免疫应答和增加造血活性。

公开(公告)号：US09786622B2

公开(公告)日：2017-10-10

申请号：US13277575

申请日：2011-10-20

Applicant: Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/1601 ,  H01L2224/16104 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.

公开(公告)号：US09543185B2

公开(公告)日：2017-01-10

申请号：US13309311

申请日：2011-12-01

Applicant: Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: B23Q3/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75754 ,  H01L2224/7698 ,  H01L2224/81001 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83102 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/013

Abstract: Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Abstract translation: 公开了用于半导体器件的封装加工工具和系统以及封装方法。 在一个实施例中，用于半导体器件的封装处理工具包括用于在集成电路管芯的封装工艺期间支撑封装衬底或集成电路管芯的机械结构。 机械结构包括设置在其上的低热导率材料。

公开(公告)号：US08878352B2

公开(公告)日：2014-11-04

申请号：US13357379

申请日：2012-01-24

Applicant: Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

Inventor： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/02

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

公开(公告)号：US20140048934A1

公开(公告)日：2014-02-20

申请号：US13586564

申请日：2012-08-15

Applicant: Meng-Tse Chen ,  Jung Wei Cheng ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Jung Wei Cheng ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L2224/16225

Abstract: A semiconductor device assembly includes a substrate having an area of the surface treated to form a surface roughness. A die is mounted on the substrate by a plurality of coupling members. An underfill substantially fills a gap disposed between the substrate and the die, wherein a fillet width of the underfill is substantially limited to the area of surface roughness.

Abstract translation: 半导体器件组件包括具有被处理以形成表面粗糙度的表面区域的衬底。 模具通过多个联接构件安装在基板上。 底部填充物基本上填充设置在基底和模具之间的间隙，其中底部填充物的圆角宽度基本上限于表面粗糙度的面积。

公开(公告)号：US20140042622A1

公开(公告)日：2014-02-13

申请号：US13572417

申请日：2012-08-10

Applicant: Tsai-Tsung Tsai ,  Chun-Cheng Lin ,  Ai-Tee Ang ,  Yi-Da Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Tsai-Tsung Tsai ,  Chun-Cheng Lin ,  Ai-Tee Ang ,  Yi-Da Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15321 ,  H05K3/3436 ,  H05K3/4015 ,  H05K2201/0367 ,  H01L2224/0401

Abstract: A package-on-package (PoP) device including a substrate having an array of contact pads arranged around a periphery of the substrate, a logic chip mounted to the substrate inward of the array of contact pads, and non-solder bump structures mounted on less than an entirety of the contact pads available.

Abstract translation: 一种封装封装（PoP）器件，包括具有围绕衬底的周边布置的接触焊盘阵列的衬底，安装到衬底内部的接触焊盘阵列的逻辑芯片以及安装在衬底上的非焊料凸块结构 小于可用的接触垫的整体。

公开(公告)号：US08609462B2

公开(公告)日：2013-12-17

申请号：US13272032

申请日：2011-10-12

Applicant: Meng-Tse Chen ,  Chun-Cheng Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Chun-Cheng Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/44

CPC classification number: B23Q3/18 ,  H01L21/50 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75733 ,  H01L2224/75744 ,  H01L2224/75754 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83868 ,  H01L2224/83874 ,  H01L2224/97 ,  H01L2924/3511 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.

公开(公告)号：US08520793B2

公开(公告)日：2013-08-27

申请号：US13090272

申请日：2011-04-20

Applicant: Chun-Cheng Lin ,  Ming-Shih Yu

Inventor： Chun-Cheng Lin ,  Ming-Shih Yu

IPC: H03D3/24

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091

Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

Abstract translation: 相位检测器包括第一采样单元，采样模块和相位确定模块。 第一采样单元被布置用于对第一数据输入信号进行采样，以根据第一时钟信号产生第一数据信号。 采样模块包括第二采样单元和第三采样单元。 第二采样单元被布置用于对第二数据输入信号进行采样以根据第二时钟信号产生第二数据信号。 第三采样单元被布置用于对第二数据信号进行采样以根据第一时钟信号产生第三数据信号。 相位确定模块被布置成根据第一数据信号和第三数据信号产生相位检测结果。