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    Apparatus for reducing power supply noise in an integrated circuit
    32.
    发明申请
    Apparatus for reducing power supply noise in an integrated circuit 有权
    用于降低集成电路中电源噪声的装置

    公开(公告)号：US20020125904A1

    公开(公告)日：2002-09-12

    申请号：US10062999

    申请日：2002-01-30

    Applicant: FormFactor, Inc.

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R031/26

    CPC classification number: G01R31/31721 ,  G01R31/2851 ,  G01R31/31905 ,  G01R31/31924 ,  G06F1/26

    Abstract: A power supply provides power to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal may temporarily increase due, for example, to state changes in the DUT. To limit variation (noise) in voltage at the power input terminal, a supplemental current is supplied to the power input terminal.

    Abstract translation: 电源为被测集成电路设备（DUT）的电源端子供电。 DUT在电源输入端子上对电流的需求可能由于例如DUT的状态变化而暂时增加。 为了限制电源输入端子电压的变化（噪声），补充电流被提供给电源输入端子。

    Apparatus for reducing power supply noise in an integrated circuit
    33.
    发明申请
    Apparatus for reducing power supply noise in an integrated circuit 失效

    公开(公告)号：US20020036515A1

    公开(公告)日：2002-03-28

    申请号：US10003596

    申请日：2001-10-30

    Applicant: FORMFACTOR, INC.

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R031/26

    CPC classification number: G06F1/26 ,  G01R31/31721 ,  Y10T307/50

    Abstract: A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUT's increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

    Method for testing signal paths between an integrated circuit wafer and a wafer tester
    36.
    发明申请
    Method for testing signal paths between an integrated circuit wafer and a wafer tester 失效
    用于测试集成电路晶片和晶圆测试仪之间的信号路径的方法

    公开(公告)号：US20040148122A1

    公开(公告)日：2004-07-29

    申请号：US10756477

    申请日：2004-01-12

    Applicant: FormFactor, Inc.

    Inventor： Ralph G. Whitten ,  Benjamin N. Eldridge

    IPC: G06F019/00

    CPC classification number: G01R31/3167

    Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

    Probe array and method of its manufacture
    37.
    发明申请
    Probe array and method of its manufacture 失效
    探头阵列及其制造方法

    公开(公告)号：US20040099641A1

    公开(公告)日：2004-05-27

    申请号：US10302969

    申请日：2002-11-25

    Applicant: FormFactor, Inc.

    Inventor： Gaetan L. Mathieu ,  Benjamin N. Eldridge ,  Gary W. Grube

    IPC: B23H001/00 ,  B23H009/00

    CPC classification number: B23H9/00 ,  G01R1/07314

    Abstract: A method of forming a probe array includes forming a layer of tip material over a block of probe material. A first electron discharge machine (EDM) electrode is positioned over the layer of tip material, the EDM electrode having a plurality of openings corresponding to a plurality of probes to be formed. Excess material from the layer of tip material and the block of probe material is removed to form the plurality of probes. A substrate having a plurality of through holes corresponding to the plurality of probes is positioned so that the probes penetrate the plurality of through holes. The substrate is bonded to the plurality of probes. Excess probe material is removed so as to planarize the substrate.

    Abstract translation: 形成探针阵列的方法包括在探针材料块上形成尖端材料层。 第一电子放电机（EDM）电极位于尖端材料层上方，EDM电极具有与要形成的多个探针对应的多个开口。 去除从尖端材料层和探针材料块的多余材料以形成多个探针。 具有对应于多个探针的多个通孔的基板被定位成使得探针穿透多个通孔。 衬底被结合到多个探针。 去除过量的探针材料以使基底平坦化。

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