公开(公告)号：US20180145236A1

公开(公告)日：2018-05-24

申请号：US15857628

申请日：2017-12-29

Applicant: Industrial Technology Research Institute

Inventor： Yu-Wei Huang ,  Tao-Chih Chang ,  Chih-Ming Shen

IPC: H01L33/62 ,  H01L25/075 ,  H01L21/56 ,  H01L33/58

CPC classification number: H01L33/62 ,  H01L21/568 ,  H01L25/0753 ,  H01L25/0756 ,  H01L33/58 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A package structure for a light emitting device including a carrier, a plurality of package units, an interconnection structure is provided. The carrier has a carrying surface, the package units stack on the carrying surface, each of the package units has a first surface and a second surface opposite the first surface and a plurality of light emitting devices arranged in an array and embedded in the package unit. Each of the light emitting devices includes a top portion facing the carrier, a bottom portion opposite to the top portion and a first electrode on the top portion, the bottom portion of each of the plurality of light emitting devices is coplanar with the first surface of the package unit. The interconnection structure is located in the package units and includes a plurality of conductive vias passing through the corresponding package units and electrically connected between the corresponding first electrodes.

公开(公告)号：US09142473B2

公开(公告)日：2015-09-22

申请号：US13849553

申请日：2013-03-25

Applicant: Industrial Technology Research Institute

Inventor： Yin-Po Hung ,  Tao-Chih Chang

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/29 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L23/3135 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3677 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83851 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The disclosure relates to a stacked type power device module. May use the vertical conductive layer for coupling the stacked devices, the electrical transmission path may be shortened. Hence, current crowding or contact damages by employing the conductive vias or wire bonding may be alleviated.

Abstract translation: 本公开涉及一种堆叠型功率器件模块。 可以使用垂直导电层来耦合堆叠的器件，可以缩短电传输路径。 因此，可以减轻通过使用导电通孔或引线接合的电流拥挤或接触损伤。

公开(公告)号：US08866309B2

公开(公告)日：2014-10-21

申请号：US13727599

申请日：2012-12-27

Applicant: Industrial Technology Research Institute

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Yu-Wei Huang ,  Yu-Min Lin ,  Shin-Yi Huang

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L23/38 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip.

Abstract translation: 第一芯片的第一后表面朝向载体。 第一芯片的第一有源表面具有第一焊盘和其上的第一绝缘层。 第二芯片设置在第一芯片上并电连接到载体。 第二芯片的第二有源表面朝向第一有源表面。 第二活性表面在其上具有第二垫和第二绝缘层。 碰撞连接第一和第二垫。 第一和第二菊花链电路分别设置在第一和第二绝缘层上。 异质热电元件对设置在第一和第二芯片之间并且由第一和第二菊花链电路串联连接，并且构成具有外部装置的电路。 第一和第二散热器分别设置在载体的第二表面和第二芯片的第二后表面上。

公开(公告)号：US20140097534A1

公开(公告)日：2014-04-10

申请号：US13736088

申请日：2013-01-08

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Tung-Han Chuang ,  Chun-Yen Lee

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29005 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83065 ,  H01L2224/8309 ,  H01L2224/83091 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/206 ,  H01L2924/00014

Abstract: Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.

Abstract translation: 提供了一种双相金属间互连结构及其制造方法。 双相金属间互连结构包括第一金属间化合物，第二金属间化合物，第一焊料层和第二焊料层。 第二金属间化合物覆盖并围绕第一金属间化合物。 第一金属间化合物和第二金属间化合物含有不同的高熔点金属。 第一焊料层和第二焊料层分别设置在第二金属间化合物的相对侧。 第一金属间化合物适于填充在形成第二金属间化合物期间产生的微孔缺陷。

公开(公告)号：US11776867B2

公开(公告)日：2023-10-03

申请号：US17839500

申请日：2022-06-14

Applicant: Industrial Technology Research Institute

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/495 ,  H01L23/373 ,  H01L23/433

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L23/3731 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/3121 ,  H01L2224/26175 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

公开(公告)号：US20210066257A1

公开(公告)日：2021-03-04

申请号：US16735707

申请日：2020-01-07

Applicant: Industrial Technology Research Institute

Inventor： Wei-Kuo Han ,  Jing-Yao Chang ,  Tao-Chih Chang

IPC: H01L25/07 ,  H01L23/498

Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.

公开(公告)号：US20200075519A1

公开(公告)日：2020-03-05

申请号：US16553179

申请日：2019-08-28

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/31

Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

公开(公告)号：US20190252345A1

公开(公告)日：2019-08-15

申请号：US16264689

申请日：2019-02-01

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/00 ,  H01L27/146

CPC classification number: H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L27/14636 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16014 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/8192 ,  H01L2224/81951 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106

Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

公开(公告)号：US20180358307A1

公开(公告)日：2018-12-13

申请号：US16108272

申请日：2018-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32503 ,  H01L2224/33505 ,  H01L2924/014 ,  H01L2924/3512

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

公开(公告)号：US20180233477A1

公开(公告)日：2018-08-16

申请号：US15487754

申请日：2017-04-14

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29076 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8381 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.