公开(公告)号：US20190181099A1

公开(公告)日：2019-06-13

申请号：US16302420

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L23/552 ,  H01P3/00 ,  H01L23/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66 ,  H01P11/00

CPC classification number: H01L23/552 ,  H01L21/8252 ,  H01L23/5225 ,  H01L23/66 ,  H01L27/0605 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2223/6627 ,  H01P3/003 ,  H01P11/003

Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).

公开(公告)号：US20190172938A1

公开(公告)日：2019-06-06

申请号：US16258422

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20190165106A1

公开(公告)日：2019-05-30

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/20 ,  H01L29/06 ,  H01L29/04 ,  H01L23/66 ,  H01L29/78 ,  H01L29/205 ,  H01L27/06

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20180374940A1

公开(公告)日：2018-12-27

申请号：US16110458

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Matthew V. METZ

IPC: H01L29/775 ,  H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/205 ,  H01L29/15 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/51 ,  B82Y40/00 ,  H01L29/06

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/155 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66469 ,  H01L29/78681 ,  H01L29/78696

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：US20180219087A1

公开(公告)日：2018-08-02

申请号：US15505911

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20180204842A1

公开(公告)日：2018-07-19

申请号：US15574092

申请日：2015-06-23

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Niloy MUKHERJEE ,  Rafael RIOS ,  Prashant MAJHI ,  Van H. LE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Gilbert DEWEY ,  Marko RADOSAVLJEVIC

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/786 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/108 ,  G11C13/0007 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/7869 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.

公开(公告)号：US20170229354A1

公开(公告)日：2017-08-10

申请号：US15498280

申请日：2017-04-26

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/84 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20170186598A1

公开(公告)日：2017-06-29

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20160343844A1

公开(公告)日：2016-11-24

申请号：US15229079

申请日：2016-08-04

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/04 ,  H01L29/10 ,  G06F1/16 ,  H03F3/195 ,  H01L29/66 ,  H01L21/02 ,  G06F1/18 ,  H01L29/20 ,  H03F3/213

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性晶体半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区域。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（1010）面在硅的（110）平面上。

公开(公告)号：US20160163918A1

公开(公告)日：2016-06-09

申请号：US14906542

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. Chau ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER

IPC: H01L33/06 ,  H01L33/62 ,  H01L33/20 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L27/153 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/16 ,  H01L33/20 ,  H01L33/32 ,  H01L33/325 ,  H01L33/62 ,  H01L2933/0033

Abstract: Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.

Abstract translation: 描述了在硅鳍模板上形成III-V LED结构的方法。 这些方法和结构可以包括在硅鳍片的硅（111）面上形成n掺杂的III-V层，在n掺杂的III-V层上形成量子阱层，形成p掺杂的III-V 层，然后在p掺杂的III-V层上形成欧姆接触层。