公开(公告)号：US20160163628A1

公开(公告)日：2016-06-09

申请号：US14563854

申请日：2014-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H05K1/16

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/162 ,  H01L2924/00

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

Abstract translation: 一种封装基板，包括第一部分和再分配部分。 第一部分被配置为作为电容器工作。 第一部分包括第一电介质层，电介质层中的第一组金属层，电介质层中的第一通孔，介电层中的第二组金属层和介电层中的第二通孔。 第一通孔耦合到第一组金属层。 第一通孔和第一组金属层被配置成为接地信号提供第一电路径。 第二通孔耦合到第二组金属层。 第二通孔和第二组金属层被配置成为功率信号提供第二电路径。 再分配部分包括第二介电层和一组互连。

公开(公告)号：US09294064B2

公开(公告)日：2016-03-22

申请号：US13835211

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: H03H7/01 ,  H03H7/12 ,  H05K1/16 ,  H01G4/40 ,  H03H3/00

CPC classification number: H03H7/0115 ,  H01G4/40 ,  H03H3/00 ,  H03H7/12 ,  H05K1/162 ,  H05K2201/09236 ,  Y10T29/43 ,  Y10T29/49016

Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.

Abstract translation: 平面电容器部分地包括围绕其端点之一形成螺旋形环的第一金属线和在第一金属线的环之间形成螺旋形环的第二金属线。 第一和第二金属线是共面的，形成在绝缘层上，并形成平面电容器的第一和第二板。 平面电容器可以用于形成滤波器。 这种过滤器包括形成第一螺旋形环的第一金属线，形成第二螺旋状环的第二金属线和与第一和第二金属线形成环之间的第一和第二金属线形成环的第三金属线 - 共面， 第二条金属线 滤波器还包括耦合在第一和第三金属线之间的第一电感器和耦合在第二和第三金属线之间的第二电感器。

公开(公告)号：US09269610B2

公开(公告)日：2016-02-23

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US09247647B1

公开(公告)日：2016-01-26

申请号：US14484000

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Jung Ho Yoon ,  Xiaonan Zhang ,  Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow

IPC: H01L29/00 ,  H05K1/18 ,  H01L23/498 ,  H01L49/02 ,  H03H7/01

CPC classification number: H01L28/40 ,  H01F17/0006 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/116 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4688 ,  H05K2201/094 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3rd harmonic suppression filter.

Abstract translation: 包括至少一个介电层的封装基板（或印刷电路板），第一电感结构至少部分地位于介电层，第三互连和第二电感结构中。 第一电感器结构包括第一互连，耦合到第一互连的第一通路和耦合到第一通路的第二互连。 第三互连件耦合到第一电感器结构。 第三互连被配置为提供用于接地信号的电路径。 第二电感器结构至少部分地位于电介质层中。 第二电感器耦合到第三互连。 第二电感器结构包括第四互连，耦合到第四互连的第二通路和耦合到第二通路的第五互连。 第一和第二电感器结构被配置为用作为三次谐波抑制滤波器的电容器操作。

公开(公告)号：US20160020193A1

公开(公告)日：2016-01-21

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L25/065 ,  H01L25/00 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US20150340425A1

公开(公告)日：2015-11-26

申请号：US14283980

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L49/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

公开(公告)号：US20150294933A1

公开(公告)日：2015-10-15

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US20150236681A1

公开(公告)日：2015-08-20

申请号：US14249189

申请日：2014-04-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H03K3/013 ,  H05K3/30 ,  H05K3/46 ,  G05F3/08 ,  H05K1/18 ,  H05K1/03

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

Abstract translation: 嵌入在衬底空腔中的嵌入式多端子电容器包括图案化成多个电源轨道和多个接地轨道的至少一个金属层。 基板包括外部电力网络。

公开(公告)号：US09041212B2

公开(公告)日：2015-05-26

申请号：US13787476

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Victor Adrian Chiriac ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Young Kyu Song

IPC: H01L23/48 ,  H01L23/34 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

Abstract translation: 一些实施方案提供半导体封装结构，其包括封装衬底，第一封装，耦合到第一封装的插入器和第一组通孔插入件（TVI）。 第一组TVI耦合到插入器和封装衬底。 第一组TVI被配置为提供第一包装的散热。 在一些实施方案中，半导体封装结构还包括耦合到插入件的散热器。 散热器被配置为从第一包装散发热量。 在一些实施方式中，第一组TVI被进一步配置成在第一封装和封装衬底之间提供电路径。 在一些实施方案中，第一封装通过插入器和第一组TVI电耦合到封装衬底。 在一些实施方案中，第一组TVI包括电介质层和金属层。

公开(公告)号：US20150048480A1

公开(公告)日：2015-02-19

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。