公开(公告)号：US09859245B1

公开(公告)日：2018-01-02

申请号：US15269514

申请日：2016-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/54

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L21/54 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/01 ,  H01L24/11 ,  H01L24/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/11849 ,  H01L2224/16013 ,  H01L2224/16104 ,  H01L2224/16221 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.

公开(公告)号：US20170345795A1

公开(公告)日：2017-11-30

申请号：US15238725

申请日：2016-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Chung Yang ,  An-Jhih Su ,  Hsien-Wei Chen ,  Jo-Mei Wang ,  Wei-Yu Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.

公开(公告)号：US09825007B1

公开(公告)日：2017-11-21

申请号：US15208764

申请日：2016-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/83

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, and the second molding layer.

公开(公告)号：US20160336289A1

公开(公告)日：2016-11-17

申请号：US15219357

申请日：2016-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L24/25 ,  H01L21/743 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.

Abstract translation: 在一些实施例中，本公开涉及具有层间互连结构的集成芯片，其具有水平部件，其布置在半导体衬底内并且被配置为将第一器件层电耦合到第二器件层。 集成芯片具有带有第一半导体衬底的第一器件层。 第一层间互连结构设置在第一半导体衬底的内部。 第一层间互连结构具有沿第一方向延伸的第一段和在基本上垂直于第一方向的第二方向从第一段的侧壁向外突出的第二段。 第二设备层通过第一层间互连结构电耦合到第一设备层。

公开(公告)号：US20250149488A1

公开(公告)日：2025-05-08

申请号：US18585599

申请日：2024-02-23

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wei-Yu Chen ,  Chao-Wei Chiu ,  Hsin Liang Chen ,  Hao-Jan Shih ,  Hao-Jan Pei ,  Hsiu-Jen Lin

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.

公开(公告)号：US20240136203A1

公开(公告)日：2024-04-25

申请号：US18401811

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/56 ,  G02B6/122 ,  G02B6/136 ,  G02B6/30 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L21/561 ,  G02B6/1225 ,  G02B6/136 ,  G02B6/30 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2924/1433

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

公开(公告)号：US20230335471A1

公开(公告)日：2023-10-19

申请号：US18342246

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming Shih Yeh

IPC: H01L23/485 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L23/528 ,  H01L21/683 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L23/485 ,  H01L23/5226 ,  H01L21/4857 ,  H01L21/4867 ,  H01L21/568 ,  H01L25/105 ,  H01L23/528 ,  H01L21/6835 ,  H01L23/5389 ,  H01L25/50 ,  H01L2225/1058 ,  H01L23/3128

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

公开(公告)号：US20230307375A1

公开(公告)日：2023-09-28

申请号：US18151583

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Tsung-Ding Wang ,  Jung Wei Cheng ,  Yu-Min Liang ,  Chien-Hsun Lee ,  Shang-Yun Hou ,  Wei-Yu Chen ,  Collin Jordon Fleshman ,  Kuo-Lung Pan ,  Shu-Rong Chun ,  Sheng-Chi Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H10B80/00 ,  H01L25/18 ,  H01L21/561 ,  H01L23/481 ,  H01L23/562 ,  H01L2224/16227 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0503 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/19 ,  H01L2224/211

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

公开(公告)号：US11721559B2

公开(公告)日：2023-08-08

申请号：US17664458

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20230109686A1

公开(公告)日：2023-04-13

申请号：US18064667

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  G02B6/30 ,  G02B6/122 ,  G02B6/136

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.