Method of forming a stack of packaged memory die and resulting apparatus
    31.
    发明授权
    Method of forming a stack of packaged memory die and resulting apparatus 有权
    形成堆叠的封装的存储器管芯和所产生的装置的方法

    公开(公告)号:US06445063B1

    公开(公告)日:2002-09-03

    申请号:US09420672

    申请日:1999-10-19

    IPC分类号: H01L2302

    摘要: A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a PCB board. One or more multi-conductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry. One embodiment of the multi-conductor insulating assembly includes tape (such as Kapton™ tape) on which conductors are applied. One surface of the tape is preferably adhesive so as to stick to the integrated circuit devices. When properly aligned, the conductors make contact with the terminals of the integrated circuit devices and with a multi-conductor port. There may be multiple layers of conductors where different terminals aligned in a stack are to receive different signals. Another embodiment of the multi-conductor insulating assembly includes an epoxy onto which conductors are applied. In yet another embodiment, multi-conductor insulating assembly tape is sandwiched between integrated circuit semiconductor devices. Contact pads on the tape are aligned with bond pads on the integrated circuit semiconductor devices.

    摘要翻译: 集成电路半导体器件的堆叠组件包括由PCB板支撑的集成电路半导体器件的堆叠。 一个或多个多导体绝缘组件提供集成电路半导体器件的端子与外部电路之间的接口。 多导体绝缘组件的一个实施例包括其上施加导体的带(例如Kapton TM带)。 带的一个表面优选是粘合剂,以便粘附到集成电路器件。 当正确对准时,导体与集成电路器件的端子和多导体端口接触。 可能存在多层导体,其中不同的端子在堆叠中对齐以接收不同的信号。 多导体绝缘组件的另一实施例包括在其上施加导体的环氧树脂。 在另一个实施例中,多导体绝缘组装带夹在集成电路半导体器件之间。 磁带上的接触焊盘与集成电路半导体器件上的接合焊盘对准。

    Method for supporting an integrated circuit die
    34.
    发明授权
    Method for supporting an integrated circuit die 有权
    支持集成电路管芯的方法

    公开(公告)号:US6148509A

    公开(公告)日:2000-11-21

    申请号:US141004

    申请日:1998-08-26

    IPC分类号: H01L23/495 H01R43/00

    摘要: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

    摘要翻译: 本发明的超导芯片(LOC)引线框架包括构造成覆盖在集成电路(IC)裸片的前侧表面上的双面胶带的交叉引线的组件。 每个引线的附接表面可粘合地附接到带上,并且至少一些引线被构造成延伸穿过模具的前侧表面从一个边缘基本上延伸到另一个边缘,例如相邻或相对的边缘。 结果,模具的前侧表面的大部分区域通过带子可粘附到引线上,因此模具可以以改进的方式支撑在IC封装中,并且可以将热量从模具 通过引线框架以改进的方式。