公开(公告)号：US20160240520A1

公开(公告)日：2016-08-18

申请号：US15007124

申请日：2016-01-26

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen

IPC: H01L25/16 ,  H01L21/304 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.

Abstract translation: 芯片封装包括芯片，电介质结合层，载体和再分配层。 芯片具有基板，导电焊盘和保护层。 电介质接合层位于保护层上，载体和保护层之间。 载体，介电接合层和保护层具有被配置为暴露导电垫的连通通孔。 再分配层包括连接部分和无源部件部分。 连接部分位于导电垫上，通孔的侧壁和载体的表面背离电介质结合层。 无源部件位于载体的表面上，无源部件的一端与载体表面上的连接部分连接。

公开(公告)号：US09334156B2

公开(公告)日：2016-05-10

申请号：US14747507

申请日：2015-06-23

Applicant: XINTEC INC.

Inventor： Chien-Min Lin ,  Yu-Ting Huang ,  Chen-Ning Fu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract translation: 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。

公开(公告)号：US09214579B2

公开(公告)日：2015-12-15

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US09177862B2

公开(公告)日：2015-11-03

申请号：US13727976

申请日：2012-12-27

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Hsin Kuan ,  Long-Sheng Yeou ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/48 ,  H01L23/28 ,  H01L21/82 ,  H01L23/14 ,  H01L21/683 ,  H01L21/768 ,  B81B7/00 ,  H01L23/00

CPC classification number: H01L21/82 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/14 ,  H01L23/147 ,  H01L24/08 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/80006 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L2224/82 ,  H01L2224/80 ,  H01L21/78

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract translation: 半导体堆叠结构的制造方法主要包括：将第一规格的晶片分割成多个芯片; 将芯片重新排列成晶片的第二规格，以通过多个块将芯片堆叠在第二规格的基板上; 在芯片上形成再分配层; 并执行切割处理以获得多个半导体堆叠结构。 因此，本发明允许通过使用常规设备来处理新规格的晶片，而不需要新的工厂建筑物或设备。 因此，可以及时提供芯片封装以满足电子产品的更换速度。

公开(公告)号：US09153707B2

公开(公告)日：2015-10-06

申请号：US13912792

申请日：2013-06-07

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Ying-Nan Wen ,  Tsang-Yu Liu

IPC: H01L31/0232 ,  H01L31/02 ,  H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。

公开(公告)号：US09054114B2

公开(公告)日：2015-06-09

申请号：US14290638

申请日：2014-05-29

Applicant: XINTEC INC.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08975755B2

公开(公告)日：2015-03-10

申请号：US14171734

申请日：2014-02-03

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48151 ,  H01L2224/73207 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract translation: 本公开的一个实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 电线层，其设置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中; 位于所述导线层和所述半导体基板之间的绝缘层; 设置在所述第一表面上的芯片; 以及设置在所述芯片和所述第一表面之间的导电结构。

公开(公告)号：US08900924B2

公开(公告)日：2014-12-02

申请号：US14173340

申请日：2014-02-05

Applicant: Xintec Inc.

Inventor： Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L25/00 ,  H01L21/822 ,  B81C1/00 ,  H01L21/768 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在第一芯片上的第二芯片; 从所述第一芯片的表面向所述第二芯片延伸的孔; 导电层，设置在所述第一芯片的表面上并延伸到所述孔中并电连接到所述第一芯片中的导电区域或掺杂区域; 以及设置在所述第一芯片和所述第二芯片之间的支撑体，其中所述支撑体基本上和/或完全覆盖所述孔的底部。

公开(公告)号：US10153237B2

公开(公告)日：2018-12-11

申请号：US15461334

申请日：2017-03-16

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Chia-Sheng Lin ,  Po-Han Lee ,  Wei-Luen Suen

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L23/31

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

公开(公告)号：US10152180B2

公开(公告)日：2018-12-11

申请号：US15061858

申请日：2016-03-04

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: G06F3/044 ,  H01L21/683 ,  H01L21/768 ,  G06K9/00 ,  H01L23/48 ,  H01L23/31

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.