公开(公告)号：US08742559B2

公开(公告)日：2014-06-03

申请号：US13419899

申请日：2012-03-14

Applicant: Noriyuki Takahashi

Inventor： Noriyuki Takahashi

IPC: H01L23/02 ,  H01L23/495 ,  H01L31/048 ,  H01L23/40

CPC classification number: H01L23/3142 ,  H01L21/50 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4334 ,  H01L23/495 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14621 ,  H01L31/048 ,  H01L2023/4031 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  Y02E10/50 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48471 ,  H01L2224/45099 ,  H01L2224/48465 ,  H01L2224/4554

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract translation: 为了抑制树脂密封型半导体装置的可靠性降低。 具有空腔（空间形成部分）的第一盖（构件）和第二盖（构件）被叠置并结合在一起以形成密封空间。 包括传感器芯片（半导体芯片）和空间内的电线的半导体以下列方式制造。 在密封盖之间的接合部分的密封步骤中，密封件由树脂形成，使得第二盖的整个上表面和第一盖的下表面的整体分别露出。 因此，在密封步骤中，可以减小沿第二盖的粉碎方向作用的压力。

公开(公告)号：US08686573B2

公开(公告)日：2014-04-01

申请号：US13767267

申请日：2013-02-14

Applicant: Renesas Electronics Corporation

Inventor： Shiko Shin ,  Takayuki Saito ,  Hiroshi Horibe

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/52

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L23/16 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/05 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract translation: 提供即使执行半导体器件的操作保证温度的升高，也能够实现半导体器件的可靠性提高的技术。 间隙部分设置在多个焊盘之间，并且由例如氧化硅膜或氮化硅膜构成的玻璃涂层嵌入间隙部分中。 提供玻璃涂层以便确保焊盘之间的电绝缘，并且涂覆焊盘的外边缘部分。 沟槽形成为与垫的外边缘部分的玻璃涂层的区域相邻。

公开(公告)号：US20140027919A1

公开(公告)日：2014-01-30

申请号：US13949185

申请日：2013-07-23

Applicant: Renesas Electronics Corporation

Inventor： Sadao Nakayama ,  Yoshihiro Matsuura

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/00014

Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.

Abstract translation: 一种半导体器件，其使用原始设计用于倒装芯片接合的半导体芯片，并且通过引线接合工艺组装以降低组装半导体产品的成本。 第二电极焊盘组和第四电极焊盘组位于半导体芯片的中心区域中，并且第一电极焊盘组和第三电极焊盘组相对于半导体芯片的两个长边相邻。 每个电极组的电极焊盘与多个导电线电耦合。 在互连基板中形成的布线层的布局被改变，使得引线键合的半导体器件在输入/输出信号的位置方面与倒装芯片结合的半导体器件相同。

公开(公告)号：US20140011453A1

公开(公告)日：2014-01-09

申请号：US13931684

申请日：2013-06-28

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Kuroda ,  Hideo Koike

IPC: H01L21/58 ,  H04B7/24

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0612 ,  H01L2224/06177 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4809 ,  H01L2224/48096 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48458 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/85181 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/1815 ,  H04B5/0075 ,  H04B7/24 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: Disclosed is a semiconductor device that is capable of handling multiple different high-frequency contactless communication modes and that is formed by a multi-chip structure. A first semiconductor chip, which performs interface control of high-frequency contactless communication and data processing of communications data, is mounted on a wiring board; and a second semiconductor chip, which performs another data processing of the communication data, is mounted on the first semiconductor chip. In this case, transmission pads in the first semiconductor chip are arranged at positions farther from a periphery of the chip than those of receiving pads, and the second semiconductor chip is mounted by being biased on the first semiconductor chip so as to keep away the transmission pads.

Abstract translation: 公开了能够处理多个不同的高频非接触通信模式并且由多芯片结构形成的半导体器件。 执行通信数据的高频无接点通信和数据处理的接口控制的第一半导体芯片安装在布线板上; 并且执行通信数据的另一数据处理的第二半导体芯片安装在第一半导体芯片上。 在这种情况下，第一半导体芯片中的传输焊盘布置在比接收焊盘更远离芯片周边的位置处，并且通过偏置在第一半导体芯片上来安装第二半导体芯片，以便保持传输 垫

公开(公告)号：US08476768B2

公开(公告)日：2013-07-02

申请号：US13170210

申请日：2011-06-28

Applicant: Ajay Kumar ,  Sahil S. Dabare ,  Ajay K. Gaite ,  Shyam S. Gupta

Inventor： Ajay Kumar ,  Sahil S. Dabare ,  Ajay K. Gaite ,  Shyam S. Gupta

IPC: H01H79/00

CPC classification number: H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/48 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.

Abstract translation: 芯片上的系统（SOC）包括具有第一和第二组接口焊盘的物理接口。 来自第一组的接口焊盘与来自第二组的接口焊盘交错。 另外，SOC被配置为具有具有第一和第二个性的超级管芯的操作，并且具有与接口焊盘的物理接口。 SOC使用第一个人中的第一数量的接口焊盘和第二个人中的第二数量的接口焊盘，其中第一个数量大于第二个数量。 A开关在超级管芯和物理接口之间切换信号，并且在第二个性中将信号切换到物理接口，使得第二数量的接口焊盘中的接口焊盘与不在第二个性中使用的接口焊盘交错。

公开(公告)号：US08405208B2

公开(公告)日：2013-03-26

申请号：US13365591

申请日：2012-02-03

Applicant: Kunihiro Komiya

Inventor： Kunihiro Komiya

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0612 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14104 ,  H01L2224/1413 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Abstract translation: 半导体器件具有CSP结构，并且包括：形成在半导体集成电路上的多个电极焊盘，用于从/从外部输入/输出信号; 用于制造外部引线电极的焊料凸块; 并重新布线。 焊料凸块沿着半导体器件的周边布置成两排。 电极焊盘配置在最外侧的焊料凸块的内部，以夹在两排焊料凸点之间。 重新布线的每个迹线从电极焊盘延伸，并且连接到任何一个最外面的焊料凸块或任何一个内部焊料凸块。

公开(公告)号：US08330272B2

公开(公告)日：2012-12-11

申请号：US12832376

申请日：2010-07-08

Applicant: Belgacem Haba

Inventor： Belgacem Haba

IPC: H01L23/52 ,  H01L23/498

CPC classification number: H01L23/48 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/0612 ,  H01L2224/114 ,  H01L2224/11472 ,  H01L2224/116 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17515 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/81893 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract translation: 封装的微电子元件包括具有前表面的微电子元件和远离前表面延伸的多个第一固体金属柱。 衬底具有主表面和多个导电元件，其暴露在主表面处并且连接到第一固体金属柱。 在具体示例中，导电元件可以是接合焊盘，或者可以是第二柱，其具有从基本角度延伸的顶表面和边缘表面。 每个第一固体金属柱包括邻近微电子元件的基底区域和远离微电子元件的尖端区域，基部区域和尖端区域具有相应的凹形圆周表面。 每个第一固体金属柱具有水平尺寸，其是在基底区域中的垂直位置的第一函数，并且其是尖端区域中垂直位置的第二函数。

公开(公告)号：US20120235308A1

公开(公告)日：2012-09-20

申请号：US13419899

申请日：2012-03-14

Applicant: Noriyuki TAKAHASHI

Inventor： Noriyuki TAKAHASHI

IPC: H01L23/52 ,  H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3142 ,  H01L21/50 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4334 ,  H01L23/495 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14621 ,  H01L31/048 ,  H01L2023/4031 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  Y02E10/50 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48471 ,  H01L2224/45099 ,  H01L2224/48465 ,  H01L2224/4554

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract translation: 为了抑制树脂密封型半导体装置的可靠性降低。 具有空腔（空间形成部分）的第一盖（构件）和第二盖（构件）被叠置并结合在一起以形成密封空间。 包括传感器芯片（半导体芯片）和空间内的电线的半导体以下列方式制造。 在密封盖之间的接合部分的密封步骤中，密封件由树脂形成，使得第二盖的整个上表面和第一盖的下表面的整体分别露出。 因此，在密封步骤中，可以减小沿第二盖的粉碎方向作用的压力。

公开(公告)号：US08237470B2

公开(公告)日：2012-08-07

申请号：US12957520

申请日：2010-12-01

Applicant: Hsian-Feng Liu ,  Eer-Wen Tyan

Inventor： Hsian-Feng Liu ,  Eer-Wen Tyan

IPC: H01L25/00

CPC classification number: H03K19/0175 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is selectively connected to an electric wire to couple to a predetermined voltage, and each of the signal pads is also selectively connected to a signal wire to transceive signals.

Abstract translation: 提供了应用于芯片或集成电路的通用IO单元。 通用IO单元包括功率垫和用于提供不同功能的多个信号垫。 根据通用IO单元的功能要求，焊盘功率选择性地连接到电线以耦合到预定电压，并且每个信号焊盘也选择性地连接到信号线以收发信号。

公开(公告)号：US20120018725A1

公开(公告)日：2012-01-26

申请号：US13181053

申请日：2011-07-12

Applicant: Tomoya NODA ,  Shigeki NAGASE

Inventor： Tomoya NODA ,  Shigeki NAGASE

IPC: H01L29/40

CPC classification number: H01L29/41741 ,  H01L22/14 ,  H01L22/32 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/423 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A FET for driving an electric motor includes a source electrode. The source electrode has main electrode surfaces to which bonding wires, through which a drive current for an electric motor passes, are joined, and inspection electrode surfaces that are arranged so as to be independent of and apart from the main electrode surfaces. The inspection electrode surfaces are provided so as to contact a probe of an inspection device that performs an inspection of the FET 3.

Abstract translation: 用于驱动电动机的FET包括源电极。 源极电极具有主电极表面，电动机的驱动电流通过的接合线通过该电极表面，并且被配置为与主电极表面独立并且与主电极表面分离的检查电极表面。 检查电极表面设置成与执行FET 3的检查的检查装置的探针接触。