公开(公告)号：US11862469B2

公开(公告)日：2024-01-02

申请号：US17709434

申请日：2022-03-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC分类号： H01L21/304 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/28 ,  H01L21/02 ,  H01L21/67 ,  H01L21/78 ,  H01L21/683 ,  B28D5/00 ,  H01L23/498

CPC分类号： H01L21/3043 ,  B28D5/00 ,  H01L21/02109 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/023 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/19011 ,  H01L2924/19106 ,  H01L2924/3511

摘要： A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure.

公开(公告)号：US11855066B2

公开(公告)日：2023-12-26

申请号：US17743455

申请日：2022-05-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC分类号： H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L21/4857 ,  H01L21/563 ,  H01L22/14 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/23 ,  H01L24/24 ,  H01L2224/02379 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  Y02P80/30 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

公开(公告)号：US11854989B2

公开(公告)日：2023-12-26

申请号：US17167789

申请日：2021-02-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dongho Kim ,  Jongbo Shim ,  Hwan Pil Park ,  Choongbin Yim ,  Jungwoo Kim

IPC分类号： H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

摘要： A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

公开(公告)号：US11854877B2

公开(公告)日：2023-12-26

申请号：US17215493

申请日：2021-03-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jing-Cheng Lin ,  Ying-Ching Shih ,  Pu Wang ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L21/76877 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/0655 ,  H01L2924/13091 ,  H01L2924/00

摘要： Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20230411363A1

公开(公告)日：2023-12-21

申请号：US18210091

申请日：2023-06-15

申请人： WALTON ADVANCED ENGINEERING, INC.

发明人： HONG-CHI YU ,  CHUN-JUNG LIN ,  RUEI-TING GU

IPC分类号： H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L23/5389 ,  H01L23/3107 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/107

摘要： A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.

公开(公告)号：US11842993B2

公开(公告)日：2023-12-12

申请号：US18064690

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC分类号： H01L27/01 ,  H01L21/70 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L25/10

CPC分类号： H01L27/013 ,  H01L21/705 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2225/1035 ,  H01L2225/1058

摘要： A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20230395573A1

公开(公告)日：2023-12-07

申请号：US18366747

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsien-Wei Chen ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/544 ,  H01L21/768 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L24/08 ,  H01L23/481 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L21/76898 ,  H01L21/6835 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/80 ,  H01L25/50 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2223/54426

摘要： A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

公开(公告)号：US11837587B2

公开(公告)日：2023-12-05

申请号：US17567169

申请日：2022-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC分类号： H01L25/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/211 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1433 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012

摘要： A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US11837550B2

公开(公告)日：2023-12-05

申请号：US17215079

申请日：2021-03-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L23/5384 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/83 ,  H01L2021/6006 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/27334 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1533 ,  H01L2924/15311 ,  H01L2224/19 ,  H01L2224/83005

摘要： A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20230378075A1

公开(公告)日：2023-11-23

申请号：US18230829

申请日：2023-08-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/3128 ,  H01L25/105 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L24/83 ,  H01L2924/1533 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/143 ,  H01L2924/141 ,  H01L2224/92244 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/27334 ,  H01L2224/214 ,  H01L24/32 ,  H01L2021/6006

摘要： A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.