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公开(公告)号:US20180145141A1
公开(公告)日:2018-05-24
申请号:US15862742
申请日:2018-01-05
IPC分类号: H01L29/423 , H01L21/3215 , H01L29/66 , H01L29/51 , H01L21/28 , H01L29/788 , H01L29/41
CPC分类号: H01L29/42324 , H01L21/28273 , H01L21/3215 , H01L29/413 , H01L29/42368 , H01L29/4238 , H01L29/51 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
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32.
公开(公告)号:US09978847B2
公开(公告)日:2018-05-22
申请号:US15454184
申请日:2017-03-09
发明人: Julien Delalleau , Christian Rivero
IPC分类号: H01L29/76 , H01L29/423 , H01L29/66 , H01L21/306 , H01L29/78 , H01L21/02 , H01L21/28 , H01L21/311 , H01L29/08
CPC分类号: H01L29/4236 , H01L21/02236 , H01L21/28167 , H01L21/30604 , H01L21/31111 , H01L29/0847 , H01L29/42368 , H01L29/42376 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.
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公开(公告)号:US20180138293A1
公开(公告)日:2018-05-17
申请号:US15809863
申请日:2017-11-10
IPC分类号: H01L29/66 , H01L29/78 , H01L21/265 , H01L29/739 , H01L21/8234 , H01L29/423 , H01L29/417 , H01L29/40 , H01L29/36 , H01L29/16 , H01L29/10 , H01L29/08 , H01L27/088 , H01L29/06
CPC分类号: H01L29/66734 , H01L21/26506 , H01L21/823412 , H01L21/823437 , H01L21/823475 , H01L21/823487 , H01L27/088 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1033 , H01L29/1095 , H01L29/16 , H01L29/36 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/7395 , H01L29/7803 , H01L29/7813 , H01L29/7827 , H01L29/7831 , H01L29/7835
摘要: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
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公开(公告)号:US20180130892A1
公开(公告)日:2018-05-10
申请号:US15862738
申请日:2018-01-05
IPC分类号: H01L29/423 , H01L21/3215 , H01L29/66 , H01L29/51 , H01L21/28 , H01L29/788 , H01L29/41
CPC分类号: H01L29/42324 , H01L21/28273 , H01L21/3215 , H01L29/413 , H01L29/42368 , H01L29/4238 , H01L29/51 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
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公开(公告)号:US09966472B2
公开(公告)日:2018-05-08
申请号:US15494680
申请日:2017-04-24
申请人: FUJITSU LIMITED
发明人: Junichi Yamaguchi
IPC分类号: H01L21/02 , H01L29/786 , H01L29/16 , H01L21/78
CPC分类号: H01L29/78606 , B82Y10/00 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02491 , H01L21/02502 , H01L21/02527 , H01L21/0262 , H01L21/02636 , H01L21/02664 , H01L21/7806 , H01L29/1606 , H01L29/42368 , H01L29/42376 , H01L29/4908 , H01L29/517 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78603 , H01L29/78684 , H01L29/78696 , H01L51/0045 , H01L51/0533 , H01L51/0558
摘要: A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr2O3. Thereby, at the time of transfer of the graphene, polymeric materials such as a resist are prevented from directly coming into contact with the graphene and nonessential carrier doping on the graphene caused by a polymeric residue of the resist is suppressed.
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公开(公告)号:US20180122931A1
公开(公告)日:2018-05-03
申请号:US15858730
申请日:2017-12-29
IPC分类号: H01L29/78 , H01L29/423 , H01L29/04 , H01L29/66 , H01L21/04 , H01L29/167 , H01L29/16 , H01L29/10 , H01L29/06 , H01L29/861
CPC分类号: H01L29/7805 , H01L21/046 , H01L29/045 , H01L29/0688 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/167 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/66734 , H01L29/78 , H01L29/7804 , H01L29/7813 , H01L29/861
摘要: According to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in the semiconductor body. Each device cell includes: a body region arranged between a source region and the drift region; a diode region and a pn junction between the diode region and the drift region; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; and a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric. The diode regions together with the drift region act as a JFET, which has a channel region in the drift region between the diode regions. The drift region has a locally increased doping concentration in the channel region of the JFET.
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37.
公开(公告)号:US09960268B2
公开(公告)日:2018-05-01
申请号:US15288243
申请日:2016-10-07
CPC分类号: H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/167 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要: A semiconductor device includes a drift region of a device structure arranged in a semiconductor layer. The drift region includes at least one first drift region portion and at least one second drift region portion. A majority of dopants within the first drift region portion are a first species of dopants having a diffusivity less than a diffusivity of phosphor within the semiconductor layer. Further, a majority of dopants within the second drift region portion are a second species of dopants. Additionally, the semiconductor device includes a trench extending from a surface of the semiconductor layer into the semiconductor layer. A vertical distance of a border between the first drift region portion and the second drift region portion to the surface of the semiconductor layer is larger than 0.5 times a maximal depth of the trench and less than 1.5 times the maximal depth of the trench.
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公开(公告)号:US20180108729A1
公开(公告)日:2018-04-19
申请号:US15843444
申请日:2017-12-15
发明人: Yongxi Zhang , Philip L. Hower , John Lin , Guru Mathur , Scott G. Balster , Constantin Bulucea , Zachary K. Lee , Sameer P. Pendharkar
IPC分类号: H01L29/06 , H01L29/78 , H01L29/10 , H01L23/485 , H01L29/423
CPC分类号: H01L29/063 , H01L23/485 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.
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公开(公告)号:US09947790B2
公开(公告)日:2018-04-17
申请号:US15416739
申请日:2017-01-26
申请人: Sony Corporation
IPC分类号: H01L29/78 , H01L21/265 , H01L29/08 , H01L29/16 , H01L29/165 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号: H01L29/7848 , H01L21/26513 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/42368 , H01L29/495 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
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公开(公告)号:US09947786B2
公开(公告)日:2018-04-17
申请号:US14942527
申请日:2015-11-16
发明人: Young Bae Kim , Kwang Il Kim
IPC分类号: H01L29/78 , H01L29/80 , H01L29/808 , H01L29/417 , H01L29/40 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号: H01L29/7832 , H01L27/085 , H01L29/063 , H01L29/0649 , H01L29/0688 , H01L29/1045 , H01L29/1058 , H01L29/1066 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/66659 , H01L29/66901 , H01L29/7835 , H01L29/808
摘要: The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.
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