公开(公告)号：US5107312A

公开(公告)日：1992-04-21

申请号：US668984

申请日：1991-03-12

申请人： William E. O'Mara, Jr. ,  James D. Beasom

发明人： William E. O'Mara, Jr. ,  James D. Beasom

IPC分类号： H01L21/338 ,  H01L29/812

CPC分类号： H01L29/66848 ,  H01L29/812

摘要： A MESFET including a Schottky top gate which extends across the channel region between the source and drain regions and beyond two opposed sides of the dielectric isolation onto the substrate in which the device is built. The portion of the top gate which extends across the channel is disconnected from the portion which extends across the substrate beyond the dielectric isolation. This may result from the removal of the gate material at the dielectric isolation or by the portion of the gate material which is on the dielectric isolation being vertically displaced and disconnected or discontinous from the portion of the gate material which extends across the channel and that portion which extends across the substrate.

摘要翻译： 一种MESFET，包括肖特基顶栅极，其横跨源极和漏极区域之间的沟道区域延伸，并且超过介质隔离的两个相对的两侧到构成器件的衬底上。 跨越通道延伸的顶栅的部分与延伸穿过衬底的部分断开，超过介电隔离。 这可能是由于介电隔离处的栅极材料的移除或介质绝缘上的栅极材料的部分在栅极材料的延伸穿过沟道的部分被垂直移位和断开或不连续，而部分 其延伸穿过衬底。

公开(公告)号：US4261095A

公开(公告)日：1981-04-14

申请号：US968052

申请日：1978-12-11

申请人： Richard F. Dreves ,  John F. Fresia ,  Sang U. Kim ,  John J. Lajza, Jr.

发明人： Richard F. Dreves ,  John F. Fresia ,  Sang U. Kim ,  John J. Lajza, Jr.

IPC分类号： H01L21/033 ,  H01L21/22 ,  H01L21/28 ,  H01L21/331 ,  H01L21/338 ,  H01L29/47 ,  H01L29/73 ,  H01L29/872

CPC分类号： H01L29/66848 ,  H01L21/033 ,  H01L21/28 ,  H01L29/872

摘要： A method of forming a self aligned guard ring surrounding a schottky barrier diode device without requiring an enlargement of the final schottky barrier device. The method involves creating an overhanging opening in a insulator layer overlying a semiconductor body to expose the schottky contact area on the surface of the semiconductor body, depositing a diffusion barrier material such as molybdenum in the opening, the deposit being of the same size as the smallest part of the overhanging opening so that a guard ring can be formed from a vapor by diffusion around the deposited barrier material.

摘要翻译： 形成围绕肖特基势垒二极管器件的自对准保护环的方法，而不需要扩大最终的肖特基势垒器件。 该方法包括在覆盖半导体主体的绝缘体层中形成突出的开口以暴露半导体主体的表面上的肖特基接触区域，在开口中沉积诸如钼的扩散阻挡材料，沉积物的尺寸与 突出开口的最小部分，使得可以通过在沉积的阻挡材料周围扩散由蒸气形成保护环。

公开(公告)号：US3956527A

公开(公告)日：1976-05-11

申请号：US511898

申请日：1974-10-03

申请人： Ingrid E. Magdo ,  Steven Magdo

发明人： Ingrid E. Magdo ,  Steven Magdo

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L21/762 ,  H01L21/82 ,  H01L27/08 ,  H01L5/02 ,  B05D5/12

CPC分类号： H01L29/66848 ,  H01L21/28537 ,  H01L21/76202 ,  H01L21/82 ,  H01L27/0814

摘要： A planar integrated circuit structure having a dielectrically isolated Schottky Barrier contact.The structure has pockets of silicon surrounded by isolating regions of silicon dioxide extending from a planar surface, the silicon dioxide regions and silicon pockets being substantially coplanar at said surface. A layer of dielectric material, such as silicon nitride or a composite of silicon nitride over silicon dioxide, covers the surface. There is at least one opening extending through the dielectric layer to a coincident silicon pocket; the opening has larger lateral dimensions than said pocket so as to expose the pocket and a portion of the silicon dioxide region surrounding the pocket. A metallic layer in this opening forms a Schottky Barrier contact with the exposed silicon.

摘要翻译： 具有介电离子肖特基势垒接触的平面集成电路结构。

公开(公告)号：US20240194739A1

公开(公告)日：2024-06-13

申请号：US18449895

申请日：2023-08-15

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Shotaro BABA ,  Tomoaki INOKUCHI ,  Tatsuo SHIMIZU ,  Tatsuya NISHIWAKI

IPC分类号： H01L29/08 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0891 ,  H01L29/47 ,  H01L29/66848 ,  H01L29/7839

摘要： According to one embodiment, a semiconductor device include first to third electrode, a semiconductor member, a first conductive member, and a first insulating member. A second insulating region of the first insulating member includes a first face facing the third partial region of the first semiconductor region. The third insulating region of the first insulating member includes a second face facing the third partial region of the first semiconductor region. The first face includes a first end on a side of the first electrode in the first direction. The second face includes a second end on a side of the second electrode in the first direction. A second position of the second end in the second direction is different from a first position of the first end in the second direction.

公开(公告)号：US20230352304A1

公开(公告)日：2023-11-02

申请号：US18135099

申请日：2023-04-14

申请人： SCDevice LLC

发明人： Sudarsan Uppili ,  David Lee Snyder ,  Scott Joseph Alberhasky

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L29/812 ,  H01L29/872 ,  H01L29/66

CPC分类号： H01L21/26513 ,  H01L21/266 ,  H01L21/28537 ,  H01L29/8122 ,  H01L29/872 ,  H01L29/66848 ,  H01L29/66143 ,  H01L29/1608

摘要： Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

公开(公告)号：US09583614B2

公开(公告)日：2017-02-28

申请号：US14298810

申请日：2014-06-06

申请人： Acorn Technologies, Inc.

发明人： Daniel E. Grupp ,  Daniel J. Connelly

IPC分类号： H01L21/338 ,  H01L29/78 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45 ,  H01L29/47 ,  H01L29/49 ,  H01L29/66 ,  H01L29/812 ,  H01L29/786

CPC分类号： H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

摘要： A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

摘要翻译： 具有至少一个通道的钝化肖特基势垒的晶体管包括在p型衬底上的绝缘栅极结构，其中沟道位于绝缘栅极结构之下。 通道和绝缘栅极结构分别限定了从绝缘栅极结构的第一和第二侧分别延伸到绝缘栅极结构下方朝向沟道的第一和第二底切空隙区域。 钝化层包括在通道的至少一个暴露的侧壁表面上，并且金属源极和漏极端子位于通道的相应的第一和第二侧上，包括在钝化层上以及绝缘栅极结构下方的底切空隙区域内。 金属源极和漏极端子中的至少一个包括在p型衬底的价带附近具有功函数的金属。

公开(公告)号：US09406670B1

公开(公告)日：2016-08-02

申请号：US14514386

申请日：2014-10-15

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/528

CPC分类号： H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

摘要： A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.

摘要翻译： 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管通过包括铜或铝的至少一个金属层互连; 第二层包括第二晶体管，第一层由第二层覆盖，其中第二层包括直径小于200nm的多个通孔通孔，其中第二晶体管包括源极接触，源极接触包括 硅化物，其中硅化物的薄层电阻小于15欧姆/平方。

公开(公告)号：US20160133475A1

公开(公告)日：2016-05-12

申请号：US14380026

申请日：2013-09-30

申请人： Peking University

发明人： Ru Huang ,  Meng Lin ,  Zhiqiang Li ,  Xia An ,  Ming Li ,  Quanxin Yun ,  Min Li ,  Pengqiang Liu ,  Xing Zhang

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/02

CPC分类号： H01L21/28537 ,  H01L21/02052 ,  H01L21/02192 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28568 ,  H01L21/3213 ,  H01L29/66143 ,  H01L29/66848 ,  H01L29/806 ,  H01L29/812 ,  H01L29/872

摘要： The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.

摘要翻译： 本发明公开了一种基于锗的肖特基结的制备方法，包括：清洗N型锗基基材的表面，然后在表面上沉积一层CeO 2，并进一步沉积一层金属。 稀土氧化物CeO2与锗衬底接触后，Ce-O-Ge键的稳定性可以在界面形成，有利于降低界面态密度，提高界面质量，降低MIGS和 抑制费米级钉扎。 同时，与Si3N4，Al2O3，Ge3N4等的情况相比，金属和锗衬底之间的CeO2引入的隧穿电阻较小。 鉴于相对于锗衬底的优异的表面特性和较小的导带偏移，CeO 2电介质层的插入适用于制备具有低电阻率的锗基肖特基结。

公开(公告)号：US20160013208A1

公开(公告)日：2016-01-14

申请号：US14864066

申请日：2015-09-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC分类号： H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/41775 ,  H01L21/28052 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66848 ,  H01L29/66871 ,  H01L29/7835 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

摘要翻译： 公开了可调谐击穿电压RF MESFET和/或MOSFET及其制造方法。 该方法包括在下面的栅极电介质材料上形成第一条线和第二条线。 第二行具有调谐到击穿电压的宽度。 该方法还包括在第一和第二线路的侧壁上形成侧壁间隔物，使得第一和第二线路之间的空间被介电隔离物夹紧。 该方法还包括形成邻近第一线和第二线的外边缘的源极和漏极区域，以及移除至少第二线，以在第二线路的侧壁间隔物之间​​形成开口并暴露下面的栅极电介质材料。 该方法还包括在开口内的下面的栅极电介质材料上沉积材料层，以及形成与栅极结构和源极和漏极区域的接触。

公开(公告)号：US09136397B2

公开(公告)日：2015-09-15

申请号：US13906738

申请日：2013-05-31

申请人： Infineon Technologies AG

发明人： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC分类号： H01L29/80 ,  H01L29/812 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/267 ,  H01L29/872

CPC分类号： H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

摘要： A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.

摘要翻译： 提供了具有主表面的半导体本体的场效应半导体器件。 半导体本体在基本上垂直于主表面的垂直横截面中包括第一导电类型的漂移层，邻接漂移层的第一导电类型的半导体台面，基本上延伸到主表面并具有两个侧面 壁，以及布置在半导体台面旁边的第二导电类型的两个第二半导体区域。 两个第二半导体区域中的每一个至少与漂移层形成pn结。 在台面的两个侧壁中的至少一个侧面上形成整流结。 此外，提供了一种异质结半导体器件的制造方法。