公开(公告)号：US09431373B2

公开(公告)日：2016-08-30

申请号：US14572288

申请日：2014-12-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Rachid Taibi ,  Cédrick Chappaz ,  Lea Di Cioccio ,  Laurent-Luc Chapelon

IPC: H01L21/66 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Abstract translation: 三维集成结构可以包括分别包括两条金属线的两个组装的集成电路，以及穿过集成电路中的一个的至少两个空腔，并分别与两个金属线电接触地分开开放到两个位置。 空腔的尺寸可以将测量装置放置在空腔的底部，并与两个位置电接触。

公开(公告)号：US20160241168A1

公开(公告)日：2016-08-18

申请号：US15042293

申请日：2016-02-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  SOCPRA Sciences et Génie S.E.C.

Inventor： Gholamreza Mirshekari ,  Etienne Leveille ,  Luc Guy Frechette ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H02N2/18

CPC classification number: H02N2/18

Abstract: A first closed enclosure defines a cavity having an inner dimension smaller than 5 mm. At least one second resiliently deformable closed enclosure is connected in fluid communication with the first enclosure. A fluid at more than 90% in the liquid state fills the first and second enclosures. A first portion of the first enclosure is in contact with a hot source of a temperature higher than the evaporation temperature of the fluid. A second portion of the first enclosure located between the first portion and the resiliently deformable closed enclosure is in contact with a cold source at a temperature lower than the condensation temperature of the fluid. An electromechanical transducer is coupled to a deformable membrane of the resiliently deformable closed enclosure.

Abstract translation: 第一封闭的外壳限定了具有小于5mm的内部尺寸的空腔。 至少一个第二可弹性变形的封闭外壳与第一外壳流体连通地连接。 在液体状态下超过90％的流体填充第一和第二外壳。 第一外壳的第一部分与高于流体蒸发温度的温度的热源接触。 位于第一部分和可弹性变形的封闭外壳之间的第一外壳的第二部分在低于流体冷凝温度的温度下与冷源接触。 机电换能器联接到可弹性变形的封闭外壳的可变形膜。

公开(公告)号：US09412589B2

公开(公告)日：2016-08-09

申请号：US14501639

申请日：2014-09-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David Barge ,  Philippe Garnier ,  Yves Campidelli

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02609 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract translation: 集成电路包括在SOI衬底的不同区域上的NMOS晶体管和PMOS晶体管。 每个晶体管包括栅极区域，在栅极区域的侧面上的多层横向绝缘区域，同时也在衬底上。 每个多层横向绝缘区域包括远离基板倾斜的倾斜部分。 源区和漏区在衬底上，并通过相应的多层横向绝缘区与栅极区的侧面分离。 源极和漏极区域具有靠在横向绝缘区域的倾斜部分的倾斜部分。

公开(公告)号：US09411176B2

公开(公告)日：2016-08-09

申请号：US14492435

申请日：2014-09-22

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier ,  Frédéric Boeuf

IPC: G02F1/025 ,  G02F1/225 ,  G02F1/21

CPC classification number: G02F1/025 ,  G02F1/225 ,  G02F2001/212

Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.

Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。

公开(公告)号：US20160190253A1

公开(公告)日：2016-06-30

申请号：US14942566

申请日：2015-11-16

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

公开(公告)号：US20160190199A1

公开(公告)日：2016-06-30

申请号：US14587401

申请日：2014-12-31

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： François ROY ,  Frédéric LALANNE ,  Pierre Emmanuel Marie MALINGE

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14641 ,  H01L27/14689 ,  H04N5/378

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

Abstract translation: 图像传感器装置可以包括以行和列排列的图像感测像素阵列。 每个图像感测像素可以包括图像感测光电二极管，耦合到图像感测光电二极管的第一源极跟随器晶体管，以及耦合到图像感测光电二极管的开关。 每个图像传感器装置可以包括耦合到开关的第二源极跟随器晶体管，以及耦合到第一和第二源极跟随器晶体管的行选择晶体管。

公开(公告)号：US20160173003A1

公开(公告)日：2016-06-16

申请号：US14903994

申请日：2014-08-18

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stephane Monfray ,  Christophe Maitre ,  Olga Kokshagina ,  Thomas Skotnicki ,  Ulrich Soupremanien

IPC: H02N1/08

CPC classification number: H02N1/08 ,  B81B3/0021 ,  B81B3/0024 ,  B81B2203/053 ,  F01K5/02 ,  H02N1/006

Abstract: A power conversion device includes an enclosure containing one or more drops of a liquid. A capacitive electret transducer is coupled to the enclosure. In response to applied heat at a heating surface, the liquid vaporizes and then condenses on a flexible membrane of the capacitive electret transducer. The flexible membrane is displaced in response to the vaporization-condensation and the capacitive electret transducer generates an output current.

Abstract translation: 电力转换装置包括包含一滴或多滴液体的外壳。 电容驻极体换能器耦合到外壳。 响应于加热表面处的加热，液体蒸发然后在电容驻极体换能器的柔性膜上冷凝。 柔性膜响应于汽化冷凝而移位，并且电容驻极体换能器产生输出电流。

公开(公告)号：US20160172278A1

公开(公告)日：2016-06-16

申请号：US14857041

申请日：2015-09-17

Applicant: STMicroelectronics (Crolles 2) SAS ,  SOCPRA Sciences et Génie S.E.C.

Inventor： Louis-Michel Collin ,  Luc Guy Frechette ,  Sandrine Lhostis

IPC: H01L23/495 ,  H01L23/492 ,  H01L23/31 ,  H01L21/52 ,  H01L23/00 ,  H01L21/54 ,  H01L21/48 ,  H01L21/311 ,  H01L25/00 ,  H01L25/065 ,  H01L23/42 ,  H01L21/56

CPC classification number: H01L23/42 ,  H01L21/31116 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/4875 ,  H01L21/4878 ,  H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3157 ,  H01L23/3672 ,  H01L23/473 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14051 ,  H01L2224/14151 ,  H01L2224/14152 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/14517 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/27462 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/30151 ,  H01L2224/30152 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/37002 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/1415

Abstract: An assembly is made of an integrated circuit chip and a plate. At least one channel is arranged between the chip and the plate. The channel is delimited by metal sidewalls at least partially extending from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate.

Abstract translation: 组件由集成电路芯片和板制成。 在芯片和板之间布置至少一个通道。 通道由金属侧壁限定，金属侧壁至少部分地从芯片的一个表面延伸到板的相对表面。 组件被封装在包括延伸到达通道的开口的主体中。 该板可以是插入件，集成电路芯片，表面安装型支架或金属板之一。

公开(公告)号：US20160133700A1

公开(公告)日：2016-05-12

申请号：US14982852

申请日：2015-12-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sylvain BARRAUD ,  Yves MORAND

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0669 ,  H01L29/413 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696 ,  H01L51/057 ,  H01L51/444 ,  H01L2924/13061 ,  H01L2924/13086

Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.

Abstract translation: 在半导体绝缘体型衬底上制造微电子器件，该器件设置有给定类型的晶体管，其沟道结构由半导体棒形成，不同于衬底的绝缘层的电介质区域 被提供以替代面向晶体管沟道结构的绝缘层，具体用于该给定类型的晶体管。

公开(公告)号：US20160104729A1

公开(公告)日：2016-04-14

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

Abstract translation: 一种制造钉扎光电二极管的方法，包括：在第二导电类型的衬底上形成光子转换到第一导电类型的电荷的区域; 用第二导电类型的重掺杂绝缘体层涂覆所述区域; 和退火以确保掺杂剂从重掺杂绝缘体层扩散。