Abstract:
A signal gate is provided where the gate can be low impedance to allow a signal to pass or be high impedance to block it. The signal gate has two output nodes arranged such that during the blocking mode spurious signals passing through the gate by way of parasitic components are presented as common mode signals at the output nodes.
Abstract:
A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.
Abstract:
An embodiment of a position sensing system includes a signal generation circuit to generate an excitation signal according to a selected characteristic signal, a drive circuit to drive an excitation source with the excitation signal, an input circuit to receive a sensor output while driving the excitation source, a signal detection circuit to identify a component of the sensor output corresponding to the characteristic signal, and a control circuit to determine the position of the movable object as a function of the identified component of the sensor output. The positioning system may be included an electronic camera, where the movable object may be a lens. The excitation source may be a conductive coil, the excitation a magnetic field, and the sensor a magneto resistive sensor. Alternatively, the excitation source may be an optical excitation source, the excitation an optical excitation, and the sensor an optical sensor.
Abstract:
Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.
Abstract:
A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.
Abstract:
A signal gate is provided where the gate can be low impedance to allow a signal to pass or be high impedance to block it. The signal gate has two output nodes arranged such that during the blocking mode spurious signals passing through the gate by way of parasitic components are presented as common mode signals at the output nodes.
Abstract:
A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.
Abstract:
A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal. The second sigma-delta modulator may include a second noise transfer function with a magnitude minimum placed at the ultrasonic frequencies.
Abstract:
A method and a digital-to-analog converter (DAC) circuit involve forming an analog signal using charge sharing operations. The DAC circuit includes a plurality of digital components with associated parasitic capacitances. The digital components are activated based on a digital input code, such that charge is shared among the parasitic capacitances to form a first analog signal proportional to the digital input code. The digital components can also be activated based on a complementary code to form a second analog signal. The first analog signal and the second analog signal can be used to form, as a final output of the DAC circuit, an analog signal that is linearly proportional to the digital input code.
Abstract:
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.