公开(公告)号：US20080257487A1

公开(公告)日：2008-10-23

申请号：US12213321

申请日：2008-06-18

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

IPC: B32B38/10

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/141 ,  H05K1/162 ,  H05K3/007 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0191 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.

Abstract translation: 插入件2包括由多个树脂层26,34,42,52,56形成的基座10; 埋在基座10中的薄膜电容器12，包括下电极20，电容器电介质膜22和上电极24; 通过基底10形成并与薄膜电容器12的上部电极24电连接的第一贯通电极14b; 以及通过基底10形成并电连接到薄膜电容器12的下电极20的第二贯通电极14a，还包括：埋入基座10中并电连接到薄膜电容器12的各个上电极24的互连件48 多个薄膜电容器12，多个第一贯通电极14b经由互连件48与所述多个薄膜电容器12的上部电极24电连接，所述多个第一贯通电极 - 电极14b通过互连48电互连。

公开(公告)号：US07435675B2

公开(公告)日：2008-10-14

申请号：US11479400

申请日：2006-06-30

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H05K1/112 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09763 ,  H05K2203/0113 ,  H05K2203/0353 ,  H05K2203/061

Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.

Abstract translation: 将预图案化的高k电介质膜形成在支撑层上的方法。 该方法包括：提供支撑层; 提供其中示出模板开口的模板，其中显示作为预图案化高k电介质膜的图案的镜像的图案; 将模板设置在支撑层上; 在模板开口内提供高k前体材料; 固化模板开口内的高k前体材料以产生固化膜; 并且在固化之后从支撑层去除模板以将固化膜留在导电膜上。

公开(公告)号：US07429510B2

公开(公告)日：2008-09-30

申请号：US11352276

申请日：2006-02-13

Applicant: Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC: H01L21/8242 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/0568

Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. Photoimageable material is used to facilitate positioning of the capacitive dielectric being printed. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.

Abstract translation: 一种形成电容衬底的方法，其中材料的至少一个电容介电层被屏幕或喷墨印刷到导体上，然后进一步处理衬底，包括添加通孔以将所选择的元件耦合到衬底内以形成 至少两个电容器作为衬底的内部元件。 可光成像材料用于促进正在印刷的电容电介质的定位。 电容性衬底可以结合在更大的电路化衬底内，例如以形成电组件。 还提供了一种制造包括这种基板的信息处理系统的方法。

公开(公告)号：US20080197967A1

公开(公告)日：2008-08-21

申请号：US11707539

申请日：2007-02-16

Applicant: Chin-Sun Shyu ,  Chang-Sheng Chen ,  Chang-Lin Wei ,  Wei-Ting Chen

Inventor： Chin-Sun Shyu ,  Chang-Sheng Chen ,  Chang-Lin Wei ,  Wei-Ting Chen

IPC: H01C1/012

CPC classification number: H01C1/02 ,  H01C7/006 ,  H01C10/46 ,  H01C17/00 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/171

Abstract: The present invention relates to an adjustable resistor embedded in a circuit board and a method of fabricating the same. The adjustable resistor comprises a resistor with a number of connection terminals, and a number of via holes extending to contact with the resistor. The resistive value of the resistor is variable depending on the size of the via holes, the number of the via holes, or the distance between the via holes.

Abstract translation: 本发明涉及嵌入在电路板中的可调电阻器及其制造方法。 可调电阻器包括具有多个连接端子的电阻器以及延伸以与电阻器接触的多个通孔。 电阻器的电阻值根据通孔的尺寸，通孔的数量或通孔之间的距离而变化。

公开(公告)号：US20080196931A1

公开(公告)日：2008-08-21

申请号：US12010194

申请日：2008-01-22

Applicant: Sang-Chul Lee ,  Won-Cheol Bae ,  Kwan-Kyu Kim ,  Doo-Hwan Lee

Inventor： Sang-Chul Lee ,  Won-Cheol Bae ,  Kwan-Kyu Kim ,  Doo-Hwan Lee

IPC: H05K1/02 ,  H05K3/36

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/061 ,  Y10T29/49126 ,  H01L2224/82 ,  H01L2924/00

Abstract: A printed circuit board having embedded components and a method for the manufacturing of the printed circuit board are disclosed. The printed circuit board includes: an intermediary insulation layer; a first core board, in which a first component having at least one electrode formed on one side is embedded, stacked on one side of the intermediary insulation layer; a first insulation layer stacked on the first core board such that the first component is covered; a second core board, in which a second component having at least one electrode formed on one side is embedded, stacked on the other side of the intermediary insulation layer; a second insulation layer stacked on the second core board such that the second component is covered; and a first via, which penetrates the first core board and the second core board. The use of this printed circuit board allows highly integrated designs.

Abstract translation: 公开了一种具有嵌入部件的印刷电路板和印刷电路板的制造方法。 印刷电路板包括：中间绝缘层; 第一芯板，其中嵌入有在一侧形成的至少一个电极的第一部件，堆叠在中间绝缘层的一侧上; 第一绝缘层，堆叠在所述第一芯板上，使得所述第一部件被覆盖; 第二芯板，其中嵌入有形成在一侧上的至少一个电极的第二部件，堆叠在中间绝缘层的另一侧上; 第二绝缘层，堆叠在所述第二芯板上，使得所述第二部件被覆盖; 以及穿过第一芯板和第二芯板的第一通孔。 该印刷电路板的使用允许高度集成的设计。

公开(公告)号：US20080180880A1

公开(公告)日：2008-07-31

申请号：US12010622

申请日：2008-01-28

Applicant: Nobuyuki Okusawa

Inventor： Nobuyuki Okusawa

IPC: H01G9/07

CPC classification number: H01G4/33 ,  H01G4/224 ,  H01L27/016 ,  H01L28/40 ,  H03H2001/0014 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/0023 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/435

Abstract: There is disclosed a thin film capacitor and the like capable of suppressing fluctuations of a capacity, increasing a VBD, and accordingly improving a device characteristic and reliability of a product. In electronic components 1 to 4, a capacitor 11 is formed on a flat substrate 51 as a base material including a planarization layer 52 formed on the surface thereof. The capacitor 11 has a structure in which a lower conductor 21 constituted of an underlayer conductor 21a and a conductor 21b, a dielectric film 31 made of alumina or the like, a resin layer J1 mainly formed of a novolak resin or the like, a resin layer J2 mainly formed of a polyimide resin or the like, and an upper conductor 25 constituted of an underlayer conductor 25a and a conductor 25b are formed on the planarization layer 52 of the substrate 51. The resin layer J1 has an opening K1 above the lower conductor 21, and the resin layer J2 is provided with an opening K2 opened more widely than the opening K1.

Abstract translation: 公开了能够抑制容量的波动，增加BDB的薄膜电容器等，从而提高产品的器件特性和可靠性。 在电子部件1〜4中，在作为基材的平坦基板51上形成电容器11，该基材包括在其表面上形成的平坦化层52。 电容器11具有下层导体21和导体21b构成的下部导体21，由氧化铝等构成的电介质膜31，主要由酚醛清漆树脂等构成的树脂层J 1 ，主要由聚酰亚胺树脂等形成的树脂层J 2和由下层导体25a和导体25b构成的上导体25形成在基板51的平坦化层52上。树脂层J 1 在下导体21上方具有开口K 1，并且树脂层J 2设置有比开口K 1更宽的开口K 2。

公开(公告)号：US20080174938A1

公开(公告)日：2008-07-24

申请号：US12055467

申请日：2008-03-26

Applicant: John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev

Inventor： John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev

IPC: H01G4/38 ,  H01G7/00

CPC classification number: H01L23/49822 ,  H01G4/236 ,  H01G4/33 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  Y10T29/435 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.

Abstract translation: 薄膜电容器组件包括通过深和浅通孔访问的两个板。 薄膜电容器组件能够与间隔件和插入件耦合。 薄膜电容器组件也能够与多个薄膜电容器组件堆叠。 薄膜电容器组件也是计算系统的一部分。

公开(公告)号：US20080173476A1

公开(公告)日：2008-07-24

申请号：US11825169

申请日：2007-07-05

Applicant: Martin A. Cotton

Inventor： Martin A. Cotton

IPC: H05K9/00

CPC classification number: H05K1/0218 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K1/0221 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/0041 ,  H05K3/4652 ,  H05K2201/09036 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2201/09981 ,  H01L2224/0401

Abstract: Construction of printed circuit boards (PCBs) containing electromagnetic shielding and conductive tubes forming signal lines and/or waveguides. The method of construction calls for forming of grooves through layers of the PCB and coating the interior surfaces of these grooves with conductive material. These conductor-coated groove walls serve as conductive surfaces between embedded conductive surfaces on different layers. The conductive surfaces thus joined form a continuous electrically conductive surface that can be configured to act as an electromagnetic shield. Such conductive surfaces may be configured with internal conductors to act as a signal line, or without internal conductors to act as a waveguide.

Abstract translation: 构造包含电磁屏蔽和形成信号线和/或波导的导电管的印刷电路板（PCB）。 施工方法要求通过PCB的层形成凹槽，并用导电材料涂覆这些凹槽的内表面。 这些导体涂覆的槽壁用作不同层上的嵌入的导电表面之间的导电表面。 这样连接的导电表面形成连续的导电表面，该表面可配置为充当电磁屏蔽。 这样的导电表面可以配置有内部导体以用作信号线，或者不具有用作波导的内部导体。

公开(公告)号：US07402760B2

公开(公告)日：2008-07-22

申请号：US11832892

申请日：2007-08-02

Applicant: Youhong Wu

Inventor： Youhong Wu

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49165

Abstract: A multi-layer printed wiring board has a core substrate, a throughhole structure, a first interlayer insulation layer, a first via, a second interlayer insulation layer and a second via. The core substrate has a throughhole opening, and the throughhole structure is formed in the throughhole opening. The first interlayer insulation layer is formed over the core substrate. The first via is formed in the first interlayer insulation layer and has a bottom portion having a first radius. The second interlayer insulation layer is formed over the first interlayer insulation layer and the first via. The second via is formed in the second interlayer insulation layer and has a bottom portion having a second radius greater than the first radius. The first via is positioned inside a circle having a radius (D1) from a gravity center of the throughhole opening, and the radius (D1) of the circle satisfies a formula, (D1)=(R)+(r)/3, where (R) represents a radius of the throughhole opening and (r) represents the first radius of the first via.

Abstract translation: 多层印刷电路板具有核心基板，通孔结构，第一层间绝缘层，第一通孔，第二层间绝缘层和第二通孔。 核心基板具有通孔开口，并且通孔结构形成在通孔开口中。 在芯基板上形成第一层间绝缘层。 第一通孔形成在第一层间绝缘层中，并且具有第一半径的底部。 第二层间绝缘层形成在第一层间绝缘层和第一通孔之上。 第二通孔形成在第二层间绝缘层中，并且具有大于第一半径的第二半径的底部。 第一通孔位于从通孔开口重心的半径（D 1）的圆内，圆的半径（D 1）满足公式，（D 1）=（R）+（r） / 3，其中（R）表示通孔开口的半径，（r）表示第一通孔的第一半径。

公开(公告)号：US07402758B2

公开(公告)日：2008-07-22

申请号：US10683641

申请日：2003-10-09

Applicant: Dwight W. Mattix

Inventor： Dwight W. Mattix

IPC: H01R12/04 ,  H05K1/11 ,  H05K3/02 ,  H05K3/10 ,  B21B15/00 ,  B21D39/03 ,  B23P23/04 ,  B23P25/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/51 ,  Y10T29/52 ,  Y10T29/5317

Abstract: A multilayer PCB including at least one carrier, wherein the at least one carrier comprises a pseudo three-layer core. Each three-layer core includes a first metal layer, a first dielectric layer, an internal bridge layer, a second dielectric layer, and a second metal layer. The bridge layer includes a plurality of bridge pads. Each carrier includes a plurality of interlayer interconnection units for interconnecting the first and second metal layers. Each interlayer interconnection unit comprises a pair of opposed blind vias and a bridge pad disposed between, and in electrical contact with, the pair of blind vias.

Abstract translation: 包括至少一个载体的多层PCB，其中所述至少一个载体包括伪三层核。 每个三层芯包括第一金属层，第一介电层，内部桥接层，第二电介质层和第二金属层。 桥接层包括多个桥接垫。 每个载体包括用于互连第一和第二金属层的多个层间互连单元。 每个层间互连单元包括一对相对的盲孔和布置在该一对盲孔之间并与该一对盲通孔电接触的桥接垫。