公开(公告)号：US09040427B2

公开(公告)日：2015-05-26

申请号：US14043818

申请日：2013-10-01

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Huma Ashraf ,  Anthony Barker

IPC: H01L21/302 ,  C23F1/12 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/308

CPC classification number: C23F1/12 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/3081

Abstract: A method of plasma etching a silicon carbide workpiece includes forming a mask on a surface of the silicon carbide workpiece, performing an initial plasma etch on the masked surface using a first set of process conditions, wherein the plasma is produced using an etchant gas mixture which includes i) oxygen and ii) at least one fluorine rich gas which is present in the etchant gas mixture at a volume ratio of less than 50%, and subsequently performing a bulk plasma etch process using a second set of process conditions which differ from the first set of process conditions.

Abstract translation: 等离子体蚀刻碳化硅工件的方法包括在碳化硅工件的表面上形成掩模，使用第一组工艺条件在掩模表面上进行初始等离子体蚀刻，其中使用蚀刻剂气体混合物 包括i）氧和ii）以等于50％的体积比存在于蚀刻剂气体混合物中的至少一种富含氟的气体，并且随后使用与第二组工艺条件不同的第二组工艺条件进行本体等离子体蚀刻工艺 第一套工艺条件。

公开(公告)号：US20140352889A1

公开(公告)日：2014-12-04

申请号：US14285730

申请日：2014-05-23

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： OLIVER ANSELL ,  BRIAN KIERNAN ,  TOBY JEFFERY ,  MAXIME VARVARA

IPC: H01L21/02

CPC classification number: H01L21/02019 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32633 ,  H01J37/32862

Abstract: An apparatus for processing a semiconductor workpiece includes a first chamber having a first plasma production source and a first gas supply for introducing a supply of gas into the first chamber, a second chamber having a second plasma production source and a second gas supply for introducing a supply of gas into the second chamber, a workpiece support positioned in the second chamber, and a plurality of gas flow pathway defining elements for defining a gas flow pathway in the vicinity of the workpiece when positioned on the workpiece support. The gas flow path defining elements include at least one wafer edge region protection element for protecting the edge of the wafer and/or a region outwardly circumjacent to the edge of the wafer, and at least one auxiliary element spaced apart from the wafer edge region protection element to define the gas flow pathway.

Abstract translation: 一种用于处理半导体工件的设备包括具有第一等离子体生产源和用于将气体供应引入第一室的第一气体供应的第一室，具有第二等离子体生产源和第二气体供应源的第二室， 将气体供应到第二室中，位于第二室中的工件支撑件以及多个气体流动通道限定了用于在定位在工件支撑件上时在工件附近限定气体流动通道的元件。 气流通道限定元件包括至少一个晶片边缘区域保护元件，用于保护晶片的边缘和/或向外周向于晶片的边缘的区域，以及至少一个与晶片边缘区域保护隔开的辅助元件 元素来定义气体流动路径。

公开(公告)号：US08728953B2

公开(公告)日：2014-05-20

申请号：US13965254

申请日：2013-08-13

Applicant: SPTS Technologies Limited

Inventor： Stephen R Burgess ,  Anthony P Wilby

IPC: H01L21/31

CPC classification number: H01L21/02104 ,  C23C14/34 ,  C23C16/455 ,  H01L21/67109 ,  H01L21/67253

Abstract: A method of processing a semiconductor workpiece includes placing a back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, and the back surface is in fluid communication with a back region having an associated back gas pressure. The method further includes performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1−Pc1, and performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively.

Abstract translation: 一种处理半导体工件的方法包括将工件的后表面放置在腔室中的工件支撑件上，使得工件的前表面面向腔室进行加工，并且后表面与具有 相关的后气体压力。 该方法还包括以第一室压Pc1和第一背压Pb1执行工件处理步骤，其中Pc1和Pb1产生压差Pb1-Pc1，并在第二室压力Pc2下执行工件冷却步骤， 第二背压Pb2，其中Pc2和Pb2分别高于Pc1和Pb1。

公开(公告)号：US20130137195A1

公开(公告)日：2013-05-30

申请号：US13674482

申请日：2012-11-12

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Oliver James Ansell

IPC: H01L21/60

CPC classification number: H01J37/32963 ,  B81C99/0065 ,  B81C2201/0135 ,  B81C2201/0142 ,  H01J37/32972 ,  H01L22/26

Abstract: A method of etching the whole width of a substrate to expose buried features is disclosed. The method includes etching a face of a substrate across its width to achieve substantially uniform removal of material; illuminating the etched face during the etch process; applying edge detection techniques to light reflected or scattered from the face to detect the appearances of buried features; and modifying the etch in response to the detection of the buried feature. An etching apparatus for etching substrate across its width to expose buried is also disclosed.

Abstract translation: 公开了一种蚀刻衬底的整个宽度以暴露掩埋特征的方法。 该方法包括在其宽度上蚀刻衬底的表面以实现材料的基本上均匀的去除; 在蚀刻过程中照射蚀刻的面; 将边缘检测技术应用于从脸部反射或散射的光，以检测埋藏特征的外观; 以及响应于所述掩埋特征的检测来修改所述蚀刻。 还公开了一种用于蚀刻衬底跨越其宽度以暴露掩埋的蚀刻装置。

公开(公告)号：US20250046604A1

公开(公告)日：2025-02-06

申请号：US18607494

申请日：2024-03-17

Applicant: SPTS Technologies Limited

Inventor： Giorgos ANTONIOU ,  Kathrine CROOK

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/455 ,  C23C16/458 ,  C23C16/505 ,  C23C16/52

Abstract: Plasma enhanced chemical vapour deposition (PECVD) is used to deposit silicon nitride onto a semiconductor substrate. A stack of silicon nitride layers are deposited onto a rear surface of the semiconductor substrate by PECVD. The stack of silicon nitride layers comprises at least four layers of silicon nitride which alternate between tensile layers which are subject to a tensile stress and compressive layers which are subject to a compressive stress.

公开(公告)号：US20250006537A1

公开(公告)日：2025-01-02

申请号：US18393632

申请日：2023-12-21

Applicant: SPTS Technologies Limited

Inventor： Adam S. BEACHEY

IPC: H01L21/683 ,  H01J37/32 ,  H01L21/3065

Abstract: During a plasma etching of a semiconductor substrate, a cooling gas is supplied to a lower surface of the semiconductor substrate at an associated pressure. The electrostatic chuck is switched between a first bipolar mode of operation in which a positive voltage is applied to a first electrode and a negative voltage is applied to a second electrode and a second bipolar mode of operation in which a negative voltage is applied to the first electrode and a positive voltage is applied to the second electrode. The pressure of the cooling gas is reduced when the ESC is switched between the first and second bipolar modes of operation with respect to the pressure at other times during the plasma etching so that the semiconductor substrate remains positioned on the substrate support.

公开(公告)号：US20240096616A1

公开(公告)日：2024-03-21

申请号：US18232313

申请日：2023-08-09

Applicant: SPTS Technologies Limited

Inventor： Matt Edmonds ,  William Royle ,  Caitlin Lane Jones ,  Daniel Gomez-Sanchez ,  Kathrine Crook

IPC: H01L21/02 ,  C23C16/52 ,  H01J37/32 ,  H01L23/498

CPC classification number: H01L21/02274 ,  C23C16/52 ,  H01J37/32165 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02216 ,  H01L23/49894 ,  H01J2237/3321

Abstract: Silicon dioxide can be deposited onto a substrate by plasma enhanced chemical vapour deposition (PECVD). The substrate includes at least one silicon dioxide layer deposited thereon. A plasma enhanced chemical vapour deposition apparatus can be used to deposit silicon dioxide onto a substrate by plasma enhanced chemical vapour deposition.

公开(公告)号：US11769675B2

公开(公告)日：2023-09-26

申请号：US16399193

申请日：2019-04-30

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Gautham Ragunathan ,  David Tossell ,  Oliver Ansell

IPC: H01L21/67 ,  H01L21/3065 ,  H01L21/687 ,  H01J37/32 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/67069 ,  H01J37/32623 ,  H01J37/32715 ,  H01L21/3065 ,  H01L21/6831 ,  H01L21/6836 ,  H01L21/68721 ,  H01L21/68778 ,  H01L21/68785 ,  H01L21/78 ,  H01L21/67092 ,  H01L2221/68327

Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.

公开(公告)号：US11643744B2

公开(公告)日：2023-05-09

申请号：US17357406

申请日：2021-06-24

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： John MacNeil ,  Martin Ayres ,  Trevor Thomas

IPC: C25D17/00 ,  C25D17/06 ,  H01L21/67 ,  H01L21/677 ,  H01L21/687 ,  H01L21/288

CPC classification number: C25D17/001 ,  C25D17/004 ,  C25D17/06 ,  H01L21/6719 ,  H01L21/6723 ,  H01L21/67178 ,  H01L21/67196 ,  H01L21/67766 ,  H01L21/67769 ,  H01L21/67778 ,  H01L21/68707 ,  H01L21/2885

Abstract: A method of processing a semiconductor wafer is provided. The method includes introducing the wafer to a main chamber via a loading port, using a transfer mechanism to transfer the wafer to a first wafer processing module in a stack so that the wafer is disposed substantially horizontally in the first wafer processing module with a front face facing upwards, and performing a processing step on the front face of the wafer in the first wafer processing module.

公开(公告)号：US20230136705A1

公开(公告)日：2023-05-04

申请号：US17976798

申请日：2022-10-29

Applicant: SPTS Technologies Limited

Inventor： Scott Haymore ,  Adrian Thomas ,  Tony Wilby ,  Stephen Burgess

IPC: H01L33/00 ,  H01L33/50

Abstract: A substrate is positioned on a substrate supporting upper surface of a substrate support. An arrangement of permanent magnets is positioned beneath the substrate supporting upper surface so that permanent magnets are disposed underneath the substrate. The deposition material is deposited into the recesses formed in the substrate by sputtering a sputtering material from a target of a magnetron device. While depositing the deposition material, the arrangement of permanent magnets provides a substantially uniform lateral magnetic field across the surface of the substrate which extends into a region beyond a periphery of the substrate to enhance resputtering of deposited material deposited into the recesses.