公开(公告)号：US07005648B2

公开(公告)日：2006-02-28

申请号：US10719117

申请日：2003-11-21

申请人： Charles Edward Baumgartner ,  David Francis Fobare ,  Michael Clement DeJule ,  Ching-Yeu Wei ,  William Andrew Hennessy ,  Robert John Wojnarowski

发明人： Charles Edward Baumgartner ,  David Francis Fobare ,  Michael Clement DeJule ,  Ching-Yeu Wei ,  William Andrew Hennessy ,  Robert John Wojnarowski

IPC分类号： G01T1/202

CPC分类号： G01T1/2928 ,  G01T1/2002

摘要： The present invention provides an X-ray detector assembly and a fabrication method, where the X-ray detector assembly comprises a scintillator material disposed on a detector matrix array disposed on a detector substrate; an encapsulating coating disposed on the scintillator material; a moisture resistant cover disposed over the detector substrate and the encapsulating coating, and an adhesive material disposed between the detector substrate and the moisture resistant cover so as to form a moisture vapor barrier. The adhesive material is disposed so that it is not in contact with the encapsulating coating. The fabrication method of the X-ray detector assembly includes the steps of disposing the encapsulating coating on the scintillator material and a portion of the detector substrate and removing the encapsulating coating from the portion of the detector substrate.

公开(公告)号：US06720561B2

公开(公告)日：2004-04-13

申请号：US10003839

申请日：2001-12-06

申请人： Charles Edward Baumgartner ,  David Francis Fobare ,  Michael Clement DeJule ,  Ching-Yeu Wei ,  William Andrew Hennessy ,  Robert John Wojnarowski ,  Haleh Ardebili ,  William Edward Burdick, Jr.

发明人： Charles Edward Baumgartner ,  David Francis Fobare ,  Michael Clement DeJule ,  Ching-Yeu Wei ,  William Andrew Hennessy ,  Robert John Wojnarowski ,  Haleh Ardebili ,  William Edward Burdick, Jr.

IPC分类号： G01T124

CPC分类号： G01T1/2928 ,  G01T1/2002

摘要： The present invention provides an X-ray detector assembly and a fabrication method, where the X-ray detector assembly comprises a scintillator material disposed on a detector matrix array disposed on a detector substrate; an encapsulating coating disposed on the scintillator material; a moisture resistant cover disposed over the detector substrate and the encapsulating coating, and an adhesive material disposed between the detector substrate and the moisture resistant cover so as to form a moisture vapor barrier. The adhesive material is disposed so that it is not in contact with the encapsulating coating. The fabrication method of the X-ray detector assembly includes the steps of disposing the encapsulating coating on the scintillator material and a portion of the detector substrate and removing the encapsulating coating from the portion of the detector substrate.

摘要翻译： 本发明提供一种X射线检测器组件和制造方法，其中X射线检测器组件包括设置在设置在检测器基板上的检测器矩阵阵列上的闪烁体材料; 设置在闪烁体材料上的封装涂层; 设置在检测器基板和封装涂层之上的防潮盖，以及设置在检测器基板和防潮盖之间的粘合材料，以形成湿气阻挡层。 粘合剂材料被设置成使其不与封装涂层接触。 X射线检测器组件的制造方法包括以下步骤：将封装涂层设置在闪烁体材料和检测器基板的一部分上，并从检测器基板的部分移除封装涂层。

公开(公告)号：US06297459B1

公开(公告)日：2001-10-02

申请号：US09019304

申请日：1998-02-05

申请人： Robert John Wojnarowski ,  Herbert Stanley Cole ,  Theresa Ann Sitnik-Nieters ,  Wolfgang Daum

发明人： Robert John Wojnarowski ,  Herbert Stanley Cole ,  Theresa Ann Sitnik-Nieters ,  Wolfgang Daum

IPC分类号： H05K109

CPC分类号： H05K1/024 ,  H05K3/386 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0158 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

摘要： A low dielectric constant printed circuit board includes: a low dielectric constant porous polymer layer having holes therethrough, the porous layer having pores; and a patterned metallization layer over surfaces of the low dielectric constant porous polymer layer and surfaces of the holes, the patterned metallization layer not significantly protruding into the pores of the porous layer.

摘要翻译： 低介电常数印刷电路板包括：具有穿过其中的孔的低介电常数多孔聚合物层，多孔层具有孔; 以及在低介电常数多孔聚合物层的表面和孔的表面上的图案化金属化层，图案化金属化层不会显着地突出到多孔层的孔中。

公开(公告)号：US06242282B1

公开(公告)日：2001-06-05

申请号：US09411101

申请日：1999-10-04

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

公开(公告)号：US06229203B1

公开(公告)日：2001-05-08

申请号：US09312537

申请日：1999-05-24

申请人： Robert John Wojnarowski

发明人： Robert John Wojnarowski

IPC分类号： H01L23495

CPC分类号： H01L25/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165

摘要： A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to a selected portion of the substrate metallization.

摘要翻译： 电路模块包括至少一个具有芯片焊盘的高温半导体芯片; 具有衬底金属化的衬底，所述芯片焊盘和所述衬底金属化基本上是平面的; 以及沉积的能够耐受高温并且耦合所选芯片焊盘和衬底金属化部分的电导体的柔性图案。 电导体的沉积的柔性图案包括多个整体的互连区段，整体互连区段中的至少一个包括第一和第二腿部部分以及搁架部分，搁架部分与至少一个半导体芯片和衬底间隔开，并且 通过第一腿部部分耦合到选定的芯片焊盘，并且由第二支腿部分耦合到衬底金属化的选定部分。

公开(公告)号：US6002163A

公开(公告)日：1999-12-14

申请号：US217334

申请日：1998-12-21

申请人： Robert John Wojnarowski

发明人： Robert John Wojnarowski

IPC分类号： F21K99/00 ,  H01L21/304 ,  H01L21/768 ,  H01L21/78 ,  H01L23/485 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L21/3043 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/10 ,  H01L25/0652 ,  H01L2224/02371 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/3511

摘要： Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

摘要翻译： 通过在器件活性区域之间形成穿过半导体晶片的孔来将顶部焊盘电气重新定位。 在晶片的所有暴露的表面上形成电绝缘层，包括在孔内，并且在绝缘层中形成开口以进入顶部互连焊盘。 晶片和孔被金属化和图案化以形成通过在孔内延伸的金属化而电连接到相应顶部互连焊盘的底部互连焊盘。 采用具有小于孔的直径的切口宽度的切割锯来分离各个装置。 为了准确地重新排列的模具的位置对准，诸如突出销或蛋箱结构的对准结构与模具接合，并且对准焊盘可以在模具上图案化。

公开(公告)号：US5938452A

公开(公告)日：1999-08-17

申请号：US922018

申请日：1997-09-02

申请人： Robert John Wojnarowski

发明人： Robert John Wojnarowski

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L23/32 ,  H01L23/485 ,  H01L23/498 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K1/14 ,  H05K3/10

CPC分类号： H01L24/02 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H05K3/3436 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K2201/0373 ,  H05K2201/10257 ,  H05K2201/10378 ,  H05K3/326 ,  H05K3/4092 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T428/24917

摘要： A flexible film interface includes a flexible film; flexible material attached to a portion of the flexible film; surface metallization on the flexible material, the flexible film having at least one via extending therethrough to the surface metallization; and a floating pad structure including floating pad metallization patterned over the flexible material and the surface metallization, a first portion of the floating pad metallization forming a central pad and a second portion of the floating pad metallization forming at least one extension from the central pad and extending into the at least one via.

公开(公告)号：US5849623A

公开(公告)日：1998-12-15

申请号：US862672

申请日：1997-05-23

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Kyung Wook Paik ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Kyung Wook Paik ,  Michael Gdula

IPC分类号： H01C1/032 ,  H01C7/00 ,  H01C17/075 ,  H01L23/538 ,  H05K1/02 ,  H05K1/16 ,  H05K3/38 ,  H01L21/20

CPC分类号： H05K1/167 ,  H01C1/032 ,  H01C17/075 ,  H01C7/006 ,  H01L2224/73204 ,  H01L2224/82039 ,  H01L23/5389 ,  H01L2924/01077 ,  H05K1/0268 ,  H05K2201/0317 ,  H05K2203/0361 ,  H05K2203/171 ,  H05K3/388 ,  Y10S148/136 ,  Y10T29/49101

摘要： A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

摘要翻译： 一种用于制造薄膜电阻器的方法包括在介电层上施加氮化钽层，在氮化钽层上施加金属化层，以及使金属化层的第一部分与金属化层的第二部分分开， 金属化层，并且第一和第二部分至少部分地位于氮化钽层上。 在一个实施例中，在图案化金属化层之后，确定金属化层的第一和第二部分之间的电阻值并将其与预定电阻值进行比较，并且修剪第一和第二部分中的至少一个以获得改良电阻 第一和第二部分之间的值比所确定的电阻值更接近于预定电阻值。

公开(公告)号：US5785787A

公开(公告)日：1998-07-28

申请号：US561990

申请日：1995-11-22

申请人： Robert John Wojnarowski ,  Herbert Stanley Cole ,  Theresa Ann Sitnik-Nieters ,  Wolfgang Daum

发明人： Robert John Wojnarowski ,  Herbert Stanley Cole ,  Theresa Ann Sitnik-Nieters ,  Wolfgang Daum

IPC分类号： H05K1/02 ,  H05K1/09 ,  H05K3/38 ,  B32B31/12 ,  B32B31/14

CPC分类号： H05K1/024 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0158 ,  H05K3/386 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

摘要： A method for fabricating a low dielectric constant printed circuit board includes dispersing an additive material in a low dielectric constant porous polymer layer; providing holes through the low dielectric constant porous polymer layer; applying a metallization layer over surfaces of the low dielectric constant porous polymer layer and surfaces of the holes; patterning the metallization layer; and removing the additive material from the low dielectric constant porous polymer layer. The removal of the additive material can be accomplished by sublimation, evaporation, and diffusion.

摘要翻译： 一种制造低介电常数印刷电路板的方法，包括将添加剂材料分散在低介电常数多孔聚合物层中; 通过低介电常数多孔聚合物层提供孔; 在低介电常数多孔聚合物层的表面和孔的表面上施加金属化层; 图案化金属化层; 并从低介电常数多孔聚合物层中除去添加剂材料。 添加剂的去除可以通过升华，蒸发和扩散来实现。

公开(公告)号：US5737458A

公开(公告)日：1998-04-07

申请号：US408236

申请日：1995-03-22

申请人： Robert John Wojnarowski ,  Herbert Stanley Cole ,  John Lawrence Henkes

发明人： Robert John Wojnarowski ,  Herbert Stanley Cole ,  John Lawrence Henkes

IPC分类号： B29D11/00 ,  G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  G02B6/36 ,  G02B6/42 ,  G02B6/43 ,  G02B6/132 ,  G02B6/30

CPC分类号： B29D11/00701 ,  G02B6/1221 ,  G02B6/13 ,  G02B6/421 ,  G02B6/43 ,  G02B2006/12173 ,  G02B2006/12176

摘要： HDI fabrication techniques are employed to form a variety of optical waveguide structures in polymer materials. Adaptive optical connections are formed, taking into account the actual position and orientation of devices which may deviate from the ideal. Structures include solid light-conducting structures, hollow light-conducting structures which are also suitable for conducting cooling fluid, and optical switching devices employing liquid crystal material. A "shrink back" method may be used to form a tunnel in polymer material which is then filled with an uncured polymer material that shrinks upon curing.