公开(公告)号：US20190267316A1

公开(公告)日：2019-08-29

申请号：US16408314

申请日：2019-05-09

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Mark T. BOHR ,  Patrick MORROW

IPC: H01L23/498 ,  H01L23/528 ,  H01L49/02

Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

公开(公告)号：US20190252525A1

公开(公告)日：2019-08-15

申请号：US16396088

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7782 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20190006296A1

公开(公告)日：2019-01-03

申请号：US15749026

申请日：2015-09-27

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Paul B. FISCHER

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01L21/845 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1211 ,  H01L28/00 ,  H01L28/10 ,  H01L2924/1206

Abstract: An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices.

公开(公告)号：US20180226478A1

公开(公告)日：2018-08-09

申请号：US15747719

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Uygar E. AVCI ,  David L. KENCKE ,  Patrick MORROW ,  Kerryann FOLEY ,  Stephen M. CEA ,  Rishabh MEHANDRU

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.

公开(公告)号：US20180219075A1

公开(公告)日：2018-08-02

申请号：US15747119

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20180219012A1

公开(公告)日：2018-08-02

申请号：US15747692

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Donald W. NELSON ,  Stephen M. CEA

IPC: H01L27/108

CPC classification number: H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087

Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

公开(公告)号：US20170077389A1

公开(公告)日：2017-03-16

申请号：US15122911

申请日：2014-06-16

Applicant: INTEL CORPORATION

Inventor： Donald W. NELSON ,  M Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0694 ,  H01L27/101 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.

Abstract translation: 一种方法，包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连，其中形成多个第一互连中的一个和多个第二互连包括嵌入存储器件 其中。 一种装置，包括在包括多个电路装置的集成电路装置层的相对侧上包括多个第一互连和多个第二互连的基板，其中多个第一互连和多个第二互连中的一个包括存储装置 嵌入其中。

公开(公告)号：US20240332301A1

公开(公告)日：2024-10-03

申请号：US18129871

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Caleb BARRETT ,  Prashant WADHWA ,  Chun-Kuo HUANG ,  Conor P. PULS ,  Daniel James HARRIS ,  Giorgio MARIOTTINI ,  Patrick MORROW

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.

公开(公告)号：US20240162141A1

公开(公告)日：2024-05-16

申请号：US18419015

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Rishabh MEHANDRU

IPC: H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/16 ,  H01L29/0653

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US20230369399A1

公开(公告)日：2023-11-16

申请号：US18225440

申请日：2023-07-24

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Anh PHAN ,  Aaron LILAK ,  Willy RACHMADY ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Richard SCHENKER ,  Hui Jae YOO ,  Patrick MORROW

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.