公开(公告)号：US06888714B2

公开(公告)日：2005-05-03

申请号：US10305767

申请日：2002-11-27

申请人： Thomas M. Shaw ,  W. David Pricer ,  Deborah A. Neumayer ,  John D. Baniecki ,  Robert B. Laibowitz

发明人： Thomas M. Shaw ,  W. David Pricer ,  Deborah A. Neumayer ,  John D. Baniecki ,  Robert B. Laibowitz

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01G4/00

CPC分类号： H01L27/0805 ,  H01L28/55

摘要： A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.

摘要翻译： 一种与半导体集成电路芯片或模块一起使用的电压旁路电容器，其包括具有机电特性的铁电电介质，其设计成在选定频率下提供最​​大损耗。

公开(公告)号：US06417572B1

公开(公告)日：2002-07-09

申请号：US09354592

申请日：1999-07-16

申请人： Dureseti Chidambarrao ,  Ronald G. Filippi ,  Robert Rosenberg ,  Thomas M. Shaw ,  Timothy D. Sullivan ,  Richard A. Wachnik

发明人： Dureseti Chidambarrao ,  Ronald G. Filippi ,  Robert Rosenberg ,  Thomas M. Shaw ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

摘要翻译： 一种制造具有绝缘钝化层的金属互连的多电平半导体器件的方法和由此产生的产品。 该产品和工艺通过防止绝缘钝化层开裂而改善金属化互连对挤出 - 短电迁移故障的阻力。 该产品和工艺也降低电阻饱和度或电迁移引起的最大电阻偏移。 通过用绝缘钝化层包围的宽线金属化互连导电线，其两个或更多个狭窄的平行导线，其纵横比小于或等于位于其间的钝化层的单位，钝化裂纹和挤出 - 短路故障的发生率是 减少 该方法特别适用于多层布线结构，其中布线层具有由冗余金属化层，层间连接或两者引起的布线水平之间的扩散障碍。

公开(公告)号：US09219037B2

公开(公告)日：2015-12-22

申请号：US13603008

申请日：2012-09-04

申请人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

发明人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

IPC分类号： B05D3/06 ,  B05D3/14 ,  C08J7/18 ,  H01L23/532 ,  C23C16/40 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02 ,  H01L21/316 ,  C23C16/511 ,  H01L21/768

CPC分类号： H01L23/5329 ,  C23C16/401 ,  C23C16/505 ,  C23C16/511 ,  C23C16/56 ,  H01J2237/336 ,  H01J2237/338 ,  H01J2237/3382 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CHx)— chains wherein x is 1, 2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.

摘要翻译： 通过在不饱和烃环境中后处理，使四面体应变增加引起的应力变化最小化的多孔SiCOH介电膜。 p-SiCOH电介质膜具有更多的（（CH x））和更少的Si-O-H和Si-H键合部分。 此外，提供稳定的pSiOCH电介质膜，其中至少在孔内的Si-OH（硅烷醇）和Si-H基团的量通过后处理减少约90％以下。 由于气孔包括其中x为1,2或3的稳定的交联 - （CH x） - 链，因此制备柔性的p-SiCOH介电膜。 介电膜是利用包括至少一个C-C双键和/或至少一个C-C三键的气态环境的退火步骤进行的。

公开(公告)号：US08841212B2

公开(公告)日：2014-09-23

申请号：US13609668

申请日：2012-09-11

申请人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

摘要翻译： 一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。 该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。 接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。 在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。 在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。

公开(公告)号：US08796133B2

公开(公告)日：2014-08-05

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US20140021622A1

公开(公告)日：2014-01-23

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US08343868B2

公开(公告)日：2013-01-01

申请号：US13005201

申请日：2011-01-12

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。

公开(公告)号：US07955955B2

公开(公告)日：2011-06-07

申请号：US11746684

申请日：2007-05-10

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L21/301

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US07678673B2

公开(公告)日：2010-03-16

申请号：US11832368

申请日：2007-08-01

申请人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

发明人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

IPC分类号： B05D3/12 ,  B05D3/06

CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

摘要翻译： 本发明提供了一种加强结构的方法，以治愈结构的缺陷，加强结构，从而加强电介质，而不影响结构的理想的低介电常数。 本发明的方法包括提供具有至少一个互连结构的半导体结构的步骤; 切割互连结构; 将至少一个渗透剂施加到所述互连结构中; 并渗透渗透剂渗透到互连结构中。

公开(公告)号：US20090035480A1

公开(公告)日：2009-02-05

申请号：US11832368

申请日：2007-08-01

申请人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

发明人： Elbert Huang ,  William F. Landers ,  Michael Lane ,  Eric G. Liniger ,  Xiao H. Liu ,  David L. Questad ,  Thomas M. Shaw

IPC分类号： B05D3/12 ,  B05D3/06

CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

摘要翻译： 本发明提供了一种加强结构的方法，以治愈结构的缺陷，加强结构，从而加强电介质，而不影响结构的理想的低介电常数。 本发明的方法包括提供具有至少一个互连结构的半导体结构的步骤; 切割互连结构; 将至少一个渗透剂施加到所述互连结构中; 并渗透渗透剂渗透到互连结构中。