公开(公告)号：US20080132053A1

公开(公告)日：2008-06-05

申请号：US11566166

申请日：2006-12-01

申请人： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

发明人： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/522 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/0476 ,  H01L2924/0479 ,  H01L2924/0475 ,  H01L2924/0474 ,  H01L2924/0483 ,  H01L2924/0496 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/048

摘要： An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

摘要翻译： 集成电路装置包括基板，包括具有位于基板上的导线的电路结构的堆叠结构，包括位于基板上的至少一个支撑构件和覆盖电路结构和支撑构件的顶板的加强结构以及至少一个 接合垫定位在屋顶上并电连接到导电线。 一种集成电路器件的制造方法，其特征在于，在基板上形成具有导线的电路结构的堆叠结构，形成包括所述基板上的至少一个支撑部件的加强结构以及覆盖所述支撑部件和所述电路结构的屋顶， 至少一个焊盘在屋顶上并且电连接到导电线。

公开(公告)号：US20080111212A1

公开(公告)日：2008-05-15

申请号：US11598391

申请日：2006-11-13

申请人： Hsiao-Che Wu

发明人： Hsiao-Che Wu

IPC分类号： H01L27/00 ,  H01L21/77

CPC分类号： H01L28/91 ,  H01L27/0805 ,  H01L27/10852

摘要： A capacitance structure of a semiconductor device and a method for manufacturing the structure are provided. The capacitance structure comprises a plurality of capacitance elements and a plurality of supports. Each of the capacitance elements has a column, and each of the supports is disposed between two adjacent columns by partially connecting onto the outer surface of each of the two adjacent columns. Thereby, the mechanical properties of the capacitance structure can be enhanced.

摘要翻译： 提供半导体器件的电容结构和制造该结构的方法。 电容结构包括多个电容元件和多个支撑件。 每个电容元件具有一列，并且每个支撑件通过部分地连接到两个相邻列中的每一个的外表面上而设置在两个相邻的列之间。 由此，可以提高电容结构的机械特性。

公开(公告)号：US20080102207A1

公开(公告)日：2008-05-01

申请号：US11715619

申请日：2007-03-08

申请人： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

发明人： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

IPC分类号： C23C16/00 ,  F16K21/00

CPC分类号： C23C16/45565 ,  C23C16/45572 ,  C23C16/481 ,  H01L21/67109 ,  H01L21/67115 ,  Y10T137/9464

摘要： A gas delivering system for an in situ thermal treatment, a thin film deposition and a use of the same are provided. The gas delivering system integrates a thermal treatment system therein so that a thin film deposition and a by rapid thermal annealing can be performed alternatively on a wafer in a reaction chamber. Accordingly, the density of the thin film can be improved and the thermal budget of the process can be reduced.

摘要翻译： 提供了一种用于原位热处理，薄膜沉积及其使用的气体输送系统。 气体输送系统将其中的热处理系统集成在一起，可以在反应室中的晶片上交替地进行薄膜沉积和快速热退火。 因此，可以提高薄膜的密度，并且可以降低该方法的热预算。

公开(公告)号：US07354837B2

公开(公告)日：2008-04-08

申请号：US11217369

申请日：2005-09-02

申请人： Chao-Hsi Chung ,  Chu-Chun Hu ,  Chih-Cheng Wang

发明人： Chao-Hsi Chung ,  Chu-Chun Hu ,  Chih-Cheng Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

摘要： A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.

摘要翻译： 提供了半导体器件的制造方法。 衬底具有带有第一栅极的阵列区域和具有第二栅极的周边区域。 依次形成由不同材料制成的第一和第二隔离层以覆盖第一栅极，第二栅极和衬底。 去除第二隔离层的一部分以在第一和第二栅极的侧壁上形成间隔物，并且在第一栅极的顶部，第二栅极的顶部和衬底的表面上暴露第一隔离层。 去除阵列区域中第一隔离层上的间隔物。 去除第一栅极的顶部上的第一隔离层和衬底的表面，从而使第一隔离层的一部分覆盖在第一栅极的侧壁上。

公开(公告)号：US20080081444A1

公开(公告)日：2008-04-03

申请号：US11599776

申请日：2006-11-14

申请人： Chin-Wen Lee

发明人： Chin-Wen Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： A method for forming a silicide layer on a silicon surface is provided. First, inert gas ions are implanted into the silicon surface. Then, a metal layer is formed on the surface and subsequently converted into the suicide layer. Thereby the resistance of the silicide can be reduced and the uniformity can be raised without substantially altering the doping concentration of conductive component(s). Thus, the efficiency of the semiconductor device can be enhanced.

摘要翻译： 提供了一种在硅表面上形成硅化物层的方法。 首先，将惰性气体离子注入硅表面。 然后，在表面上形成金属层，随后将其转化为硅化物层。 因此，可以减少硅化物的电阻，并且可以提高均匀性而基本上不改变导电组分的掺杂浓度。 因此，可以提高半导体器件的效率。

公开(公告)号：US07332387B2

公开(公告)日：2008-02-19

申请号：US11324454

申请日：2006-01-03

申请人： Chen-Liang Chu

发明人： Chen-Liang Chu

IPC分类号： H01L21/8234

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28176 ,  H01L29/42368 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced by the bird's beak structure.

摘要翻译： 描述MOSFET结构及其形成方法。 与漏极区相邻的MOSFET结构的栅极电介质层的一部分的厚度增加以形成鸟的喙结构。 通过鸟的喙结构减小了栅极到漏极的重叠电容。

公开(公告)号：US07320912B2

公开(公告)日：2008-01-22

申请号：US11125676

申请日：2005-05-10

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/8242

CPC分类号： H01L29/945 ,  H01L27/1087

摘要： A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

摘要翻译： 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US07312497B2

公开(公告)日：2007-12-25

申请号：US11143991

申请日：2005-06-02

申请人： Yi Ding

发明人： Yi Ding

IPC分类号： H01L29/788

CPC分类号： H01L29/42344 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531

摘要： In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric (302, 304, 310) formed over control gate lines (134). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

摘要翻译： 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅线（134）上形成的电介质（302,304,310）。 每个控制栅极线提供一列存储器单元的控制栅极。 用于相邻存储器列的相邻控制栅极线彼此间隔开。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

公开(公告)号：US07312131B2

公开(公告)日：2007-12-25

申请号：US10998929

申请日：2004-11-30

申请人： Hsiao-Che Wu

发明人： Hsiao-Che Wu

IPC分类号： H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10867 ,  H01L28/91 ,  H01L29/417 ,  H01L29/945

摘要： A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.

摘要翻译： 描述形成多层电极电容器的方法。 在衬底或绝缘体层中形成沟槽。 两组导电层沉积在沟槽的内表面上。 第一组导电层彼此电连接，第二组导电层也相互电连接。 第二组导电层中的每一个插入在两个第一导电层之间，并且介电层插入在两个导电层之间以形成多层电极电容器。

公开(公告)号：US20070278538A1

公开(公告)日：2007-12-06

申请号：US11553432

申请日：2006-10-26

申请人： Te-Sheng Chao

发明人： Te-Sheng Chao

IPC分类号： H01L29/768

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  Y10S257/903

摘要： A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

摘要翻译： 公开了一种相变存储单元，包括第一电极和第二电极，以及设置在第一和第二电极之间的多个记录层。 每个记录层的有源区的相位可以通过电流脉冲控制而变为结晶状态或非晶状态，因此分别具有结晶电阻或无定形电阻。 至少两个记录层具有不同的尺寸，使得晶体和非晶体电阻的不同组合在第一和第二电极之间产生至少三个不同的有效电阻值。 相变存储单元可以用相同的记录层材料实现，因此可以用简单且目前开发的CMOS制造工艺技术来制造。 此外，由于大的电流编程间隔，相变存储器易于控制。