公开(公告)号：US20190043564A1

公开(公告)日：2019-02-07

申请号：US15845500

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： ALIASGAR S. MADRASWALA ,  BHARAT M. PATHAK ,  BINH N. NGO ,  NAVEEN VITTAL PRABHU ,  KARTHIKEYAN RAMAMURTHI ,  PRANAV KALAVADE

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/5631

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

公开(公告)号：US20180350428A1

公开(公告)日：2018-12-06

申请号：US15873304

申请日：2018-01-17

Applicant: SK hynix Inc.

Inventor： Dong-Ho KANG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4072 ,  G11C8/04

CPC classification number: G11C11/40611 ,  G11C8/04 ,  G11C8/08 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4087

Abstract: A semiconductor device may include: a low-order bit storage block configured for storing N low-order bit signals contained in N access information signals based on an access address signal, the N access information signals indicating the numbers of accesses to N access target blocks, and generating an indication signal indicating whether a low-order bit signal corresponding to the current input access address signal among the N low-order bit signals has reached a predetermined value; a high-order bit storage block configured for storing M high-order bit signals contained in M access information signals among the N access information signals based on an allocation control signal; and a high-order bit control block configured for generating the allocation control signal corresponding to positions in which the M high-order bit signals are to be stored, based on the access address signal and the indication signal.

公开(公告)号：US20180308542A1

公开(公告)日：2018-10-25

申请号：US15822718

申请日：2017-11-27

Applicant: SK hynix Inc.

Inventor： Donggun KIM ,  Jung Hyun KWON ,  Yong Ju KIM ,  Do Sun HONG

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C7/10 ,  G06F12/02

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/08 ,  G11C11/5642 ,  G11C13/0023 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427

Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.

公开(公告)号：US20180261285A1

公开(公告)日：2018-09-13

申请号：US15861701

申请日：2018-01-04

Applicant: Winbond Electronics Corp.

Inventor： Norio Hattori ,  Masaru Yano

IPC: G11C13/00 ,  H01L27/24 ,  G11C8/08

CPC classification number: G11C13/004 ,  G11C8/08 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0047 ,  H01L27/24 ,  H01L2924/1438

Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

公开(公告)号：US10074430B2

公开(公告)日：2018-09-11

申请号：US15231011

申请日：2016-08-08

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.

公开(公告)号：US10074410B2

公开(公告)日：2018-09-11

申请号：US15282532

申请日：2016-09-30

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

公开(公告)号：US10062436B2

公开(公告)日：2018-08-28

申请号：US15291945

申请日：2016-10-12

Applicant: SK hynix Inc.

Inventor： Kwang-Myoung Rho

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/16 ,  G11C16/26 ,  G11C7/02 ,  G11C8/08

CPC classification number: G11C13/0064 ,  G11C7/02 ,  G11C7/08 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/08 ,  G11C11/161 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/26

Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.

公开(公告)号：US20180233203A1

公开(公告)日：2018-08-16

申请号：US15952155

申请日：2018-04-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/14 ,  G11C16/28 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  H01L27/112 ,  G11C16/10 ,  G11C7/06

CPC classification number: G11C16/14 ,  G11C7/065 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2216/04 ,  H01L27/112 ,  H01L27/11582 ,  H01L28/00

Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.

公开(公告)号：US10037819B2

公开(公告)日：2018-07-31

申请号：US15484244

申请日：2017-04-11

Applicant: SK hynix Inc.

Inventor： Jae II Kim

IPC: G11C11/402 ,  G11C29/00 ,  G11C11/406 ,  G11C8/08 ,  G11C29/52

CPC classification number: G11C29/783 ,  G11C8/08 ,  G11C11/402 ,  G11C11/40611 ,  G11C29/52

Abstract: A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.

公开(公告)号：US20180197585A1

公开(公告)日：2018-07-12

申请号：US15866156

申请日：2018-01-09

Applicant: Dolphin Integration

Inventor： Julien Louche ,  Olivier Mercier ,  Khaja Ahmad Shaik

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/10 ,  G11C7/18 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419

Abstract: A memory circuit having: a control circuit of a line of a memory array including: a first transistor coupled between first and second nodes and controlled by a line selection signal including a high level and a low level; a second transistor controlled by a first signal and coupled between the first node and a voltage supply rail of a first supply voltage, the first supply voltage being higher than the high level of the line selection signal, the first node being coupled to a line of memory array, the second node receiving a timing signal; and a line deactivation circuit adapted to generate the first signal and including a reference cell and a level shifter.