公开(公告)号：US20230377632A1

公开(公告)日：2023-11-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G11C11/4096 ,  G06F11/1048 ,  G11C7/02 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20230360695A1

公开(公告)日：2023-11-09

申请号：US18203591

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  James E. Harris

IPC: G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  G11C7/22

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C7/22

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

公开(公告)号：US11809712B2

公开(公告)日：2023-11-07

申请号：US17586575

申请日：2022-01-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

公开(公告)号：US11804259B2

公开(公告)日：2023-10-31

申请号：US17715370

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/34 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/4076

CPC classification number: G11C11/4091 ,  G06F11/10 ,  G06F11/1004 ,  G11C11/4076 ,  G11C2207/2263

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US11804250B2

公开(公告)日：2023-10-31

申请号：US17665760

申请日：2022-02-07

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US11782807B2

公开(公告)日：2023-10-10

申请号：US17744347

申请日：2022-05-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

CPC classification number: G06F11/2094 ,  G11C11/4093 ,  G11C29/52 ,  G06F2201/82

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US20230244576A1

公开(公告)日：2023-08-03

申请号：US18096812

申请日：2023-01-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G11C7/20 ,  G11C14/00 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G11C7/20 ,  G11C14/0018 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G06F2201/805 ,  G06F2201/84

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US11709736B2

公开(公告)日：2023-07-25

申请号：US17354268

申请日：2021-06-22

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/00 ,  G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  H01L25/065 ,  H01L25/10

CPC classification number: G06F11/142 ,  G06F3/0617 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/00 ,  G06F13/1673 ,  G06F13/4068 ,  H01L24/00 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  G06F11/1423 ,  G06F2201/805 ,  G06F2201/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US20230229593A1

公开(公告)日：2023-07-20

申请号：US18152642

申请日：2023-01-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/7203

Abstract: A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

公开(公告)号：US20230224101A1

公开(公告)日：2023-07-13

申请号：US18078936

申请日：2022-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L1/24 ,  H04L7/00 ,  G11C7/10 ,  H04L25/02 ,  G11C29/02 ,  H04L25/12 ,  H04L27/00 ,  H04L7/10 ,  G11C7/04 ,  H04L7/033

CPC classification number: H04L1/242 ,  H04L7/0016 ,  G11C7/1084 ,  H04L25/0292 ,  G11C29/028 ,  H04L25/12 ,  G11C29/022 ,  H04L27/00 ,  G11C7/1057 ,  H04L7/10 ,  H04L7/0091 ,  G11C29/025 ,  H04L7/0087 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.