公开(公告)号：US06333129B2

公开(公告)日：2001-12-25

申请号：US09295352

申请日：1999-04-21

申请人： Yong-hoon Kim ,  Jin-hong Park

发明人： Yong-hoon Kim ,  Jin-hong Park

IPC分类号： G03F900

CPC分类号： G03F1/29

摘要： A method of fabricating a phase shift mask is provided in which light shield film patterns for setting a phase shift region and a phase non-shift region are simultaneously formed on a substrate. A groove is formed in the substrate set as the phase shift region. The light shield film pattern, which contacts the groove and is formed on a region of the substrate set as the phase non-shift region, is removed. A phase shift layer can be formed between the substrate and the light shield film pattern. In this case, regions set by the light shield film pattern become opposite to when the phase shift layer is not formed. That is, a phase shift region is changed into a phase non-shift region, and the phase non-shift region is changed into the phase shift region. As described above, the phase shift region and the phase non-shift region are simultaneously set when the light shield film pattern is formed, thus preventing the position of the phase shift or non-shift region from being shifted due to sequential formation of the phase shift and non-shift regions.

摘要翻译： 提供一种制造相移掩模的方法，其中在衬底上同时形成用于设置相移区域和相位非移位区域的光屏蔽膜图案。 在衬底组中形成有作为相移区域的沟槽。 除去接触凹槽并形成在作为相位非移位区域的基板的区域上的遮光膜图案。 可以在基板和遮光膜图案之间形成相移层。 在这种情况下，由遮光膜图案设定的区域与没有形成相移层时相反。 也就是说，相移区域被改变为相位非移位区域，并且相位非移位区域变为相移区域。 如上所述，当形成遮光膜图形时，相移区域和相位非移位区域被同时设置，从而防止相移或非移位区域的位置由于相位的顺序形成而偏移 移位和非移位区域。

公开(公告)号：US06296975B1

公开(公告)日：2001-10-02

申请号：US09426762

申请日：1999-10-26

申请人： Seong-yong Moon ,  Yong-hoon Kim ,  Kwang-soo No

发明人： Seong-yong Moon ,  Yong-hoon Kim ,  Kwang-soo No

IPC分类号： G03F900

CPC分类号： G03F1/54

摘要： A photo mask of a semiconductor device includes a transmission preventing layer formed of a molybdenum alloy, which is a solid solution of a metal atom such as chrome in molybdenum, on a light transmitting substrate. Also, the molybdenum alloy may be a molybdenum vanadium alloy, a molybdenum niobium alloy, a molybdenum tantalum alloy, or a molybdenum tungsten alloy, which is a solid solution of vanadium, niobium, tantalum, or tungsten in molybdenum, respectively. The photo mask provides high resolution during a photolithography process by obtaining a thinner transmission preventing layer.

摘要翻译： 半导体器件的光掩模包括由钼合金形成的防透光层，其是钼等金属原子的固溶体在透光性基板上。 此外，钼合金可以分别是钼中的钒，铌，钽或钨的固溶体的钼钒合金，钼铌合金，钼钽合金或钼钨合金。 光掩模通过获得较薄的防止传播层在光刻过程中提供高分辨率。

公开(公告)号：US09566493B2

公开(公告)日：2017-02-14

申请号：US14123487

申请日：2012-06-02

申请人： Yong Hoon Kim

发明人： Yong Hoon Kim

IPC分类号： A63B69/36 ,  G06K9/00

CPC分类号： A63B69/36 ,  G06K9/00342

摘要： A housing type golf simulation apparatus and features the housing that the internal space is available having front, rear, upper and left/right side; monitor installation section which is provided backward in the rear side direction from the said front housing so that the monitor can be seated in the said front housing; golf simulation computer which is provided in the said internal space; and the monitor to be seated in the said monitor installation section. Thus, it is advantageous to implement various additional functions in the housing while installing, managing and moving the entire golf simulation apparatus in an integrated module.

摘要翻译： 一种外壳式高尔夫模拟装置，其特征在于，内部空间具有前，后，上，左/右侧的外壳; 监视器安装部，其从所述前壳体向后方设置，使得所述监视器能够坐在所述前壳体中; 设置在所述内部空间中的高尔夫模拟计算机; 并将显示器安装在所述显示器安装部分中。 因此，在集成模块中安装，管理和移动整个高尔夫模拟装置的同时，在壳体中实现各种附加功能是有利的。

公开(公告)号：US08791559B2

公开(公告)日：2014-07-29

申请号：US13604301

申请日：2012-09-05

申请人： Yong-hoon Kim ,  Hyo-soon Kang ,  Jin-kyung Kim

发明人： Yong-hoon Kim ,  Hyo-soon Kang ,  Jin-kyung Kim

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L21/50

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/1301 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.

摘要翻译： 提供了一种封装结构封装的半导体封装，减少了封装的整体厚度，并简化了布线路径的设计复杂性。 所述封装包括：第一封装，包括第一基板和安装在其上的第一半导体芯片部分;第二封装，设置在所述第一封装上，并且包括第二基板和安装在其上的第二半导体芯片部分;以及连接部件， 底物。 第二半导体芯片部分包括至少一个半导体芯片，其包括对应于一个通道的一组芯片焊盘，并且该组芯片焊盘集中在半导体芯片的第一边缘上。 对应于一个通道的知识产权核心形成在第一半导体芯片部分的边缘上，并且IP核心对应于芯片组集中的边缘。

公开(公告)号：US08680667B2

公开(公告)日：2014-03-25

申请号：US13400035

申请日：2012-02-17

申请人： Heung-Kyu Kwon ,  Seong-Ho Shin ,  Yun-Seok Choi ,  Yong-Hoon Kim

发明人： Heung-Kyu Kwon ,  Seong-Ho Shin ,  Yun-Seok Choi ,  Yong-Hoon Kim

IPC分类号： H01L23/02

CPC分类号： H01L24/06 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

摘要翻译： 封装堆叠结构可以是上封装包括具有第一边缘和与第一边缘相对的第二边缘的上封装基板。 上封装衬底具有布置在第一边缘附近的第一区域和布置在第二边缘附近的第二区域。 第一上半导体器件安装在上封装衬底上。 封装堆叠结构还可以包括具有下封装衬底和下半导体器件的下封装。 下封装通过多个封装间连接器连接到上封装。 多个包装间连接器可以包括被配置为传送数据信号的第一包装间连接器; 配置成发送地址/控制信号的第二串联连接器连接器; 第三组件间连接器，被配置为提供地址/控制电路的电源电压; 以及被配置为提供数据电路的电源电压的第四组件间连接器。

公开(公告)号：US08471613B2

公开(公告)日：2013-06-25

申请号：US12648674

申请日：2009-12-29

申请人： Yong-Hoon Kim ,  Hyun-Woo Lee

发明人： Yong-Hoon Kim ,  Hyun-Woo Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0995

摘要： An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells.

摘要翻译： 内部时钟信号发生电路能够根据外部时钟信号的频率来控制单位延迟时间。 内部时钟信号发生电路包括：内部时钟信号生成单元，被配置为产生与响应于控制信号而使能的多个单位延迟单元相对应的内部时钟信号;以及单位延迟时间控制单元， 外部时钟信号并且控制多个单元延迟单元中的每一个的单位延迟时间。

公开(公告)号：US20120306062A1

公开(公告)日：2012-12-06

申请号：US13437285

申请日：2012-04-02

申请人： Yong-Hoon KIM ,  In-Ho CHOI ,  Keung-Beum KIM

发明人： Yong-Hoon KIM ,  In-Ho CHOI ,  Keung-Beum KIM

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/5225 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on a circuit substrate. A second semiconductor package is provided on the circuit substrate and spaced apart from the first semiconductor package. An insulating electromagnetic shielding structure is provided on the top and the lateral surfaces of the first semiconductor package. A conductive electromagnetic shielding structure is provided on the circuit substrate to cover the first and second semiconductor packages and the insulating electromagnetic shielding structure.

摘要翻译： 提供半导体器件，半导体封装和电子器件。 电子设备包括设置在电路基板上的第一半导体封装。 第二半导体封装设置在电路基板上并与第一半导体封装间隔开。 绝缘电磁屏蔽结构设置在第一半导体封装的顶表面和侧表面上。 导电电磁屏蔽结构设置在电路基板上以覆盖第一和第二半导体封装和绝缘电磁屏蔽结构。

公开(公告)号：US20120049352A1

公开(公告)日：2012-03-01

申请号：US13208455

申请日：2011-08-12

申请人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

发明人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

摘要： A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

摘要翻译： 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。

公开(公告)号：US20110304015A1

公开(公告)日：2011-12-15

申请号：US13115431

申请日：2011-05-25

申请人： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

发明人： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

摘要翻译： 半导体封装包括其中形成有多根导线的基板; 至少一个半导体芯片电连接到多个导线的部分; 并且屏蔽可以安装在基板上，围绕至少一个半导体芯片，电连接到多根导线中的至少一根导线并且包括软磁性材料。 半导体封装可以防止或显着降低电磁干扰（EMI）。

公开(公告)号：US20100308865A1

公开(公告)日：2010-12-09

申请号：US12494748

申请日：2009-06-30

申请人： Yong-Hoon Kim

发明人： Yong-Hoon Kim

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： A semiconductor device includes a buffer unit configured to include first and second buffers, connected to each other in a cross-coupled manner, to receive a reference voltage and to buffer an input signal applied to the first and second buffers based on the reference voltage to drive an output terminal with a current-driving capacity; and a drive power adjustor configured to adjust the current-driving capacity depending on a level of a power supply voltage applied to the buffering unit.

摘要翻译： 半导体器件包括缓冲单元，其被配置为包括以交叉耦合方式彼此连接的第一和第二缓冲器，以接收基准电压，并且基于参考电压缓冲施加到第一和第二缓冲器的输入信号 驱动具有电流驱动能力的输出端子; 以及驱动电力调整器，被配置为根据施加到缓冲单元的电源电压的电平来调整电流驱动能力。