摘要:
A method for forming through a dielectric layer a trench contiguous with a via. There is provided a substrate having a contact region formed therein. There is then formed upon the substrate a patterned first dielectric layer defining a via accessing the contact region, where the patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed completely covering the patterned first dielectric layer and filling the via a the blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket hard mask layer a patterned photoresist layer which provides an exposed portion of the blanket hard mask layer greater that an areal dimension of the via and at least partially overlapping the areal dimension of the via. There is then implanted into the exposed portion of the blanket hard mask layer and into a portion of the blanket second dielectric layer aligned beneath the exposed portion of the blanket hard mask layer a dose of an ion to form an ion implanted portion of the blanket hard mask layer and an ion implanted portion of the blanket second dielectric layer, where the ion implanted portion of the blanket second dielectric layer has an enhanced etch rate within the oxygen containing plasma in comparison with a non ion implanted portion of the blanket second dielectric layer. There is then etched while employing a first plasma etch method the ion implanted portion of the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing a second plasma etch method employing the oxygen containing plasma the blanket second dielectric layer to form a patterned second dielectric layer having an aperture formed therethrough, where the aperture comprises a trench and at least a portion of the via.
摘要:
A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu3Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.
摘要:
In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.
摘要:
A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.
摘要:
A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second dielectric will subsequently act as an etch stop. The third dielectric is a sacrificial layer used to protect the second dielectric. Contact holes are then etched in the layers of first, second, and third dielectric. A first barrier metal and a first conductor metal are then deposited filling the contact hole. The first barrier metal and first conductor metal are then removed down to a level between the original top surface of the layer of third dielectric and the top surface of the second dielectric using a method such as chemical mechanical polishing. The sacrificial third dielectric protects the layer of second dielectric during the chemical mechanical polishing. A layer of fourth dielectric is then deposited. Trenches are then etched in the fourth dielectric using the second dielectric, which has been maintained intact by the sacrificial third dielectric, as an etch stop. The trenches are then filled with a second barrier metal and second conductor metal. Excess second barrier metal and second conductor metal are then removed using chemical mechanical polishing to complete the damascene structure.
摘要:
A method to form copper interconnects with an improved encapsulation layer is achieved. A substrate layer is provided. Conductive traces are provided overlying the substrate layer. A first intermetal dielectric layer is deposited overlying the conductive traces. The first intermetal dielectric layer is etched through to the underlying conductive traces where the first intermetal dielectric layer is not protected by a photoresist mask to form interconnect trenches. A barrier layer is deposited overlying the first intermetal dielectric layer and exposed the conductive traces. A copper layer is deposited overlying the barrier layer and filling the interconnect trenches. The copper layer and the barrier layer are polished down to the top surface of the first intermetal dielectric layer to define copper interconnects. An encapsulation layer is formed overlying the copper interconnects wherein the encapsulation layer is not formed overlying the first intermetal interconnect layer and wherein the encapsulation layer is at least partially comprised of tungsten nitride. A second intermetal dielectric layer is deposited and the fabrication of the integrated circuit device is completed.
摘要:
A method is disclosed for forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical-mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate including a composite groove/hole structure already formed in an insulating layer and then growing a copper seed layer over the barrier layer. A layer of photoresist is next deposited over the substrate filling the composite structure. The photoresist layer, seed layer and the barrier layer are then removed by chemical-mechanical polishing, leaving the seed layer and the barrier layer on the inside walls of the composite structure, however. Then the photoresist is removed from the composite structure, and replaced, in its place, with electroless plated copper, which forms a dome-like protrusion extending from the composite structure. When the substrate is subjected to chemical-mechanical polishing in order to remove the excess copper, the dome-like structure prevents the dishing of the copper metal. In a second embodiment, the seed layer and the barrier layer are chemical-mechanical polished without first depositing a photoresist layer. Copper metal is next selectively formed by electroless plating having a dome-like protrusion, which in turn is removed by chemical-mechanical polishing without the detrimental formation of dishing in the copper metal.
摘要:
Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.
摘要:
Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
摘要:
A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.