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51.发明申请公开(公告)号：US20120326329A1
公开(公告)日：2012-12-27
申请号：US13604539
申请日：2012-09-05
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/04042 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/16225 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.
摘要翻译： 半导体器件由包含由周边区域分离的半导体管芯的半导体晶片制成。 在周边区域或通过器件的有源区域形成导电通孔结构，以提供额外的拉伸强度。 导电通孔结构包括由绝缘材料隔开的内部导电通孔和外部导电通孔。 中间导电通孔可以形成在内导电通孔和外导电通孔之间。 内部导电通孔具有与半导体器件的第一表面相邻的第一横截面区域和与半导体器件的第二表面相邻的第二横截面区域。 外导电通孔具有与半导体器件的第一表面相邻的第一横截面区域和与半导体器件的第二表面相邻的第二横截面区域。 第一截面积与第二横截面积不同。
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52.发明授权Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps 有权半导体器件和用导电凸块互连的具有内部已知的良好裸芯片的PiP的形成方法公开(公告)号：US08283209B2
公开(公告)日：2012-10-09
申请号：US12635631
申请日：2009-12-10
IPC分类号： H01L21/00
CPC分类号： H01L23/49548 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/49541 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/24226 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/83411 , H01L2224/83424 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/85001 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15747 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/0105 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
摘要翻译： PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。
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公开(公告)号：US20120241939A1
公开(公告)日：2012-09-27
申请号：US13492646
申请日：2012-06-08
CPC分类号： H01L23/3121 , H01L21/568 , H01L23/3677 , H01L23/4334 , H01L24/19 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/05554 , H01L2224/12105 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/73265 , H01L2224/73267 , H01L2224/82001 , H01L2224/9222 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/30105 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer.
摘要翻译： 半导体封装包括具有接触焊盘的半导体管芯。 密封剂设置在半导体管芯周围，并且导电通孔设置在密封剂中。 导电迹线设置在接触焊盘和导电通孔之间，导热通道设置在与导电通孔分开的密封剂中，并且导热层设置在半导体管芯的发热区域上。 导热迹线设置在导热层和导热通道之间。 导热层，导热迹线和导热通道与半导体管芯和导电迹线的接触焊盘电隔离。 半导体封装还包括设置在密封剂上方的宽热痕迹，以及互连宽热导迹和导热层的导热材料。
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公开(公告)号：US08241954B2
公开(公告)日：2012-08-14
申请号：US11949133
申请日：2007-12-03
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L23/3114 , H01L24/18 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48464 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2225/06506 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/30105 , H01L2224/83 , H01L2224/82 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a wafer level chip scale package (WLCSP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLCSP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
摘要翻译： 在晶片级芯片级封装（WLCSP）中，半导体管芯具有在其有源表面上形成的有源电路和接触焊盘。 第二半导体管芯设置在第一半导体管芯上。 第一再分配层（RDL）电连接第一和第二半导体管芯。 第三半导体管芯设置在第二半导体管芯上。 第二和第三半导体管芯用粘合剂附着。 第二RDL电连接第一，第二和第三半导体管芯。 第二个RDL可以是接合线。 钝化层隔离RDL和第二和第三半导体管芯。 在WLCSP的表面上形成多个焊料凸块。 焊料凸块形成在电连接到RDL上的凸起下金属化处。 焊料凸块通过第一和第二RDL电连接到第一，第二或第三半导体管芯。
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公开(公告)号：US20110298120A1
公开(公告)日：2011-12-08
申请号：US13212986
申请日：2011-08-18
IPC分类号： H01L23/498 , H01L23/34
CPC分类号： H01L23/3121 , H01L21/568 , H01L23/3677 , H01L23/4334 , H01L24/19 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/05554 , H01L2224/12105 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/73265 , H01L2224/73267 , H01L2224/82001 , H01L2224/9222 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/30105 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer.
摘要翻译： 半导体封装包括具有接触焊盘的半导体管芯。 密封剂设置在半导体管芯周围，并且导电通孔设置在密封剂中。 导电迹线设置在接触焊盘和导电通孔之间，导热通道设置在与导电通孔分开的密封剂中，并且导热层设置在半导体管芯的发热区域上。 导热迹线设置在导热层和导热通道之间。 导热层，导热迹线和导热通道与半导体管芯和导电迹线的接触焊盘电隔离。 半导体封装还包括设置在密封剂上方的宽热痕迹，以及互连宽热导迹和导热层的导热材料。
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56.发明申请Semiconductor Device and Method of Providing a Thermal Dissipation Path Through RDL and Conductive Via 有权提供通过RDL和导电通孔的散热路径的半导体器件和方法公开(公告)号：US20110037168A1
公开(公告)日：2011-02-17
申请号：US12911042
申请日：2010-10-25
IPC分类号： H01L23/34
CPC分类号： H01L23/525 , H01L23/3677 , H01L23/5226 , H01L23/552 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48247 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/04941 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a conductive via formed around a perimeter of the semiconductor die. First and second conductive layers are formed on opposite sides of the semiconductor die and thermally connected to the conductive via. An insulating layer is formed over the semiconductor die. Openings in the insulating layer expose the first conductive layer and a thermal dissipation region of semiconductor die. A thermal via is formed through the insulating layer to the first conductive layer. A thermally conductive layer is formed over the thermal dissipation region and thermal via. A thermal conduction path is formed from the thermal dissipation region through the thermally conductive layer, thermal via, first conductive layer, conductive via, and second conductive layer. The thermal conduction path terminates in an external thermal ground point. The thermally conductive layer provides shielding for electromagnetic interference.
摘要翻译： 半导体器件具有围绕半导体管芯的周边形成的导电通孔。 第一和第二导电层形成在半导体管芯的相对侧上并与导电通孔热连接。 在半导体管芯上形成绝缘层。 绝缘层中的开口露出半导体芯片的第一导电层和散热区域。 通过绝缘层向第一导电层形成热通孔。 在散热区域和热通孔上形成导热层。 热传导路径通过导热层，热通孔，第一导电层，导电通孔和第二导电层由散热区域形成。 热传导路径终止于外部热接地点。 导热层为电磁干扰提供屏蔽。
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57.发明申请Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers 有权导电层非线性部分之间形成垂直互连结构的半导体器件和方法公开(公告)号：US20100314780A1
公开(公告)日：2010-12-16
申请号：US12484146
申请日：2009-06-12
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/568 , H01L24/19 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02333 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/16145 , H01L2224/16245 , H01L2224/32145 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/92244 , H01L2225/06513 , H01L2225/06517 , H01L2225/06558 , H01L2225/1035 , H01L2225/1058 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.
摘要翻译： 半导体器件通过在具有圆形凹槽的第一临时载体上形成第一导电层而制成。 第一导电层由于圆形的凹陷而具有非线性部分。 在第一导电层的非线性部分上形成凸块。 半导体管芯安装在载体上。 第二导电层形成在具有圆形凹槽的第二临时载体上。 第二导电层由于圆形凹陷而具有非线性部分。 第二载体安装在凸块上。 在第一半导体管芯周围的第一和第二临时载体之间沉积密封剂。 去除第一和第二载体以留下第一和第二导电层。 通过第一导电层和密封剂形成导电通孔以电连接到第一半导体管芯上的接触焊盘。
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58.发明授权Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same 有权半导体晶片级互连封装，使用用于单独电压源的导电环和焊盘及其制造方法公开(公告)号：US07838395B2
公开(公告)日：2010-11-23
申请号：US11951729
申请日：2007-12-06
IPC分类号： H01L21/00 , H01L23/48 , H01L23/52 , H01L23/04 , H01L23/482 , H01L23/535
CPC分类号： H01L24/02 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3157 , H01L23/3171 , H01L23/3185 , H01L23/528 , H01L23/5286 , H01L23/585 , H01L24/05 , H01L24/13 , H01L24/18 , H01L24/19 , H01L24/82 , H01L24/96 , H01L2224/02315 , H01L2224/02371 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05024 , H01L2224/12105 , H01L2224/13026 , H01L2224/18 , H01L2224/32145 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
摘要翻译： 半导体管芯具有在其有源表面上形成的有源电路。 接触焊盘形成在半导体管芯的有源表面上并耦合到有源电路。 在半导体管芯的周围形成管芯延伸区域。 通孔（THV）形成在管芯延伸区域中。 在半导体管芯的有源表面的中心区域形成导电平面或环。 导电平面或环耦合到第一接触焊盘，以向有源电路提供第一电源电位。 导电平面或环电连接到第一THV。 导电环部分地围绕导电平面或环的周边形成。 导电环耦合到第二接触焊盘，以向有源电路提供第二电源电位。 导电环电连接到第二THV。
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59.发明授权Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect 有权形成具有垂直互连的重构的可堆叠晶片级封装的半导体器件和方法公开(公告)号：US09177832B2
公开(公告)日：2015-11-03
申请号：US13234535
申请日：2011-09-16
申请人： Zigmund R. Camacho
发明人： Zigmund R. Camacho
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L25/10 , H01L23/00 , H01L21/56
CPC分类号： H01L21/486 , H01L21/561 , H01L21/568 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2224/03
摘要： A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.
摘要翻译： 半导体器件具有带有半导体管芯安装区域的载体。 多个导电柱形成在半导体管芯安装区域的周边和载体中。 移除载体的第一部分以暴露多个导电柱的第一部分，使得多个导电柱的第二部分嵌入载体的第二部分中。 第一半导体管芯安装到半导体管芯安装区域和多个导电柱的第一部分之间。 围绕第一半导体管芯并围绕多个导电柱的第一部分沉积第一密封剂。 移除载体的第二部分以暴露多个导电柱的第二部分。 在多个导电柱和第一半导体管芯之上形成互连结构。
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公开(公告)号：US08722457B2
公开(公告)日：2014-05-13
申请号：US11965383
申请日：2007-12-27
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L23/3128 , H01L23/3135 , H01L23/49861 , H01L23/5385 , H01L24/48 , H01L25/03 , H01L25/50 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/18165 , H01L2924/19041 , H01L2924/19104 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die.
摘要翻译： 在半导体封装中，衬底具有包含多个有源电路的有源表面。 在基板的有效表面上形成粘合剂层，并且将已知的良好单元（KGU）安装到粘合剂层上。 互连结构将KGU和衬底上的有源电路电连接。 所述互连结构包括在所述衬底上的接触焊盘和所述KGU上的接触焊盘之间的引线接合，所述衬底的背面上的与所述有源表面相对的再分布层，穿过所述衬底的通孔通孔（THV） 连接再分布层和引线键合，以及与再分布层电接触形成的焊料凸块。 KGU包括用于支撑KGU的KGU基板，设置在KGU基板上的半导体管芯，以及形成在半导体管芯上的密封剂。
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