公开(公告)号：US20140239438A1

公开(公告)日：2014-08-28

申请号：US13774541

申请日：2013-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L23/538 ,  H01L27/04 ,  H01L21/82

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US20140110858A1

公开(公告)日：2014-04-24

申请号：US13736097

申请日：2013-01-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gottfried Beer ,  Walter Hartner

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/522

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01Q1/2283 ,  H01Q23/00 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

Abstract translation: 提供一种用于制造嵌入式芯片封装的方法。 该方法可以包括：在衬底上形成导电线; 将衬底放置在包括芯片的芯片装置旁边，该芯片包括一个或多个接触焊盘，其中一个或多个导电线被布置成靠近芯片的侧壁; 以及在所述芯片布置上形成一个或多个电互连以将至少一个导电线电连接到至少一个接触垫。

公开(公告)号：US20140110840A1

公开(公告)日：2014-04-24

申请号：US13736553

申请日：2013-01-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maciej Wojnowski ,  Walter Hartner ,  Ottmar Geitner ,  Gottfried Beer ,  Klaus Pressel ,  Mehran Pour Mousavi

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17519 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01Q23/00 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01064 ,  H01L2924/01044 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract translation: 在本发明的一个实施例中，半导体封装包括具有第一主表面和相对的第二主表面的衬底。 芯片设置在基板中。 芯片包括在第一主表面处的多个接触垫。 第一天线结构设置在第一主表面处。 反射器设置在第二主表面处。

公开(公告)号：US10241088B2

公开(公告)日：2019-03-26

申请号：US15136469

申请日：2016-04-22

Applicant: Infineon Technologies AG

Inventor： Horst Theuss ,  Gottfried Beer ,  Sebastian Beer ,  Alfons Dehe ,  Franz Jost ,  Stefan Kolb ,  Guenther Ruhl ,  Rainer Markus Schaller

IPC: G01N29/24 ,  G01N29/032

Abstract: A photo-acoustic gas sensor includes a light emitter unit having a light emitter configured to emit a beam of light pulses with a predetermined repetition frequency and a wavelength corresponding to an absorption band of a gas to be sensed, and a detector unit having a microphone. The light emitter unit is arranged so that the beam of light pulses traverses an area configured to accommodate the gas. The detector unit is arranged so that the microphone can receive a signal oscillating with the repetition frequency.

公开(公告)号：US10008470B2

公开(公告)日：2018-06-26

申请号：US15628682

申请日：2017-06-21

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Walter Hartner

IPC: H01L21/00 ,  H01L21/4763 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538 ,  H01Q23/00 ,  H01Q1/22 ,  H01L23/522 ,  H01L23/498 ,  H01L23/66 ,  H01L25/16 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01Q1/2283 ,  H01Q23/00 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

公开(公告)号：US09978720B2

公开(公告)日：2018-05-22

申请号：US15201624

申请日：2016-07-05

Applicant: Infineon Technologies AG

Inventor： Horst Theuss ,  Gottfried Beer ,  Juergen Hoegerl

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/522 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.

公开(公告)号：US09721920B2

公开(公告)日：2017-08-01

申请号：US13736097

申请日：2013-01-08

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Walter Hartner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L21/00 ,  H01L21/4763 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538 ,  H01Q23/00 ,  H01Q1/22 ,  H01L23/498 ,  H01L23/66 ,  H01L25/16 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01Q1/2283 ,  H01Q23/00 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

公开(公告)号：US09620459B2

公开(公告)日：2017-04-11

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00 ,  H01L23/051 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/90 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/33181 ,  H01L2224/82039 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/35 ,  H01L2924/00

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

公开(公告)号：US09589859B2

公开(公告)日：2017-03-07

申请号：US14462693

申请日：2014-08-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/34 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L23/00 ,  H01L23/051

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract translation: 半导体装置包括多个芯片组件，每个芯片组件包括半导体芯片，半导体芯片具有顶侧和下侧的半导体主体，布置在顶侧的顶部主电极，布置在下侧的底部主电极，电气 导电顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内导电地连接到顶部主电极，导电底部补偿层布置在底部主电极的背离 半导体本体并且内导电地连接到底部主电极，以及环形化方式围绕半导体芯片横向周向的电介质嵌入化合物，使得补偿层的背离半导体本体的一侧至少不是完全的 被包埋化合物覆盖。

公开(公告)号：US20160126192A1

公开(公告)日：2016-05-05

申请号：US14529371

申请日：2014-10-31

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/00 ,  H01L25/00

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract translation: 功率半导体模块包括具有陶瓷衬底的直接铜键合（DCB）衬底，与陶瓷衬底的第一主表面接合的第一铜金属化层和与陶瓷衬底的第一主表面相对的陶瓷衬底的第二主表面接合的第二铜金属化 主表面。 功率半导体模块还包括附接第一铜金属化的功率半导体管芯，连接第一铜金属化的无源部件，封装功率半导体管芯和无源部件的第一隔离层，第一隔离层上的第一结构化金属化层， 以及从第一结构化金属化层延伸穿过第一隔离层到功率半导体管芯和无源部件的第一多个导电通孔。 还提供了集成电源模块和制造集成电源模块的方法。