公开(公告)号：US20110262868A1

公开(公告)日：2011-10-27

申请号：US13085251

申请日：2011-04-12

Applicant: Kousuke MURAKAMI ,  Akira ARIMA ,  Tomohiro HATTORI ,  Shuuhei MIYAZAKI

Inventor： Kousuke MURAKAMI ,  Akira ARIMA ,  Tomohiro HATTORI ,  Shuuhei MIYAZAKI

IPC: G03F7/20 ,  G06K9/00

CPC classification number: H05K1/0269 ,  G03F9/00 ,  H05K3/0097 ,  H05K2201/09918 ,  H05K2203/166

Abstract: When an alignment mark does not exist within an area of an image obtained by a camera, the coordinate of the alignment mark is calculated based on an identification mark existing in the area of the image and a previously stored positional relationship between the alignment mark and the identification mark. A distance by which a long-sized base material is to be moved for causing the alignment mark to be positioned within the imaging area of the camera is calculated based on the calculated coordinate of the alignment mark, and the long-sized base material is moved by the calculated distance.

Abstract translation: 当通过照相机获得的图像的区域内不存在对准标记时，基于存在于图像的区域中的识别标记和对准标记与对准标记之间的先前存储的位置关系来计算对准标记的坐标 识别标志。 基于所计算的对准标记的坐标，计算要使移动用于使对准标记位于摄像机的摄像区域内的长度的基材的距离，并且移动长尺寸的基材 按计算距离。

公开(公告)号：US08037584B2

公开(公告)日：2011-10-18

申请号：US11979833

申请日：2007-11-08

Applicant: Kwang-Soo Park ,  Sim-Hwan Park ,  Jeong-Yeon Jeong ,  Dae-Jung Byun

Inventor： Kwang-Soo Park ,  Sim-Hwan Park ,  Jeong-Yeon Jeong ,  Dae-Jung Byun

IPC: B23Q1/54 ,  B23Q3/157 ,  B23B39/02

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/0082 ,  H05K3/4652 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/0554 ,  Y10T29/49156

Abstract: A printed circuit board, a method of manufacturing the printed circuit board, and an apparatus for perforating via holes are disclosed. By use of a method of manufacturing a printed circuit board that includes forming a first circuit pattern, which includes a reference mark and a via land, on one surface of an insulation substrate; stacking a metal layer on the insulation layer; opening a first window in the metal layer in correspondence with the reference mark; and forming a via which electrically connects the via land with the metal layer, by irradiating light towards the other surface of the insulation substrate and identifying the reference mark through the first window, the occurrence of short-circuiting is prevented in forming vias for electrical interconnection between circuit patterns in a printed circuit board, and as the defect rate caused by eccentricity between insulation layers may be reduced, aspects of the invention may contribute to reducing costs.

Abstract translation: 公开了一种印刷电路板，印刷电路板的制造方法和穿孔孔的装置。 通过使用包括在绝缘基板的一个表面上形成包括参考标记和通孔接合面的第一电路图案的印刷电路板的制造方法; 在绝缘层上堆叠金属层; 与参考标记相对应地在金属层中打开第一窗口; 以及形成通孔，其通过使所述通孔接地与所述金属层电连接，通过朝向所述绝缘基板的另一表面照射光并通过所述第一窗口识别所述基准标记，在形成用于电互连的通路中防止发生短路 印刷电路板中的电路图案之间以及作为由绝缘层之间的偏心引起的缺陷率可能会降低，本发明的各方面可有助于降低成本。

公开(公告)号：US20110247511A1

公开(公告)日：2011-10-13

申请号：US13130610

申请日：2009-12-09

Applicant: Daniel H. Carlson ,  Daniel J. Theis ,  Brian K. Nelson

Inventor： Daniel H. Carlson ,  Daniel J. Theis ,  Brian K. Nelson

IPC: B41J2/01 ,  B26D3/00 ,  G03B27/00 ,  B26D3/08

CPC classification number: H05K1/0269 ,  B41J3/543 ,  B41J11/46 ,  H05K3/0082 ,  H05K2201/09918 ,  H05K2203/013 ,  H05K2203/107 ,  H05K2203/1545 ,  Y10T83/02 ,  Y10T83/0333

Abstract: Fiducials having substantially continuous portions made on a substrate allow the position of the substrate to be determined. An approach for making fiducials involves moving first and second fiducial devices together back and forth across the substrate along a trajectory having a component along the lateral axis of the substrate while the substrate and the first and second fiducial devices are in relative motion along the longitudinal axis of the substrate. The first fiducial device operates to make one fiducial on the substrate during the movement along the trajectory and the relative motion. The second fiducial device operates to make another fiducial on the substrate during the movement along the trajectory and the relative motion. The fiducials may be formed so that they have a constant spatial frequency with the first fiducial being out of phase with respect to the second fiducial.

Abstract translation: 在基板上具有基本上连续的部分的基准允许确定基板的位置。 用于制造基准的方法涉及使第一和第二基准装置沿着具有沿着基板的横向轴线的分量的轨迹穿过基板一起来回移动，同时基板和第一和第二基准装置沿着纵向轴线相对运动 的基底。 第一个基准装置用于在轨迹和相对运动的运动过程中在基板上形成一个基准点。 第二基准装置在沿着轨迹和相对运动的运动期间操作以在基底上形成另一基准。 基准可以被形成为使得它们具有恒定的空间频率，其中第一基准相对于第二基准是异相的。

公开(公告)号：US08024858B2

公开(公告)日：2011-09-27

申请号：US12351954

申请日：2009-01-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷线路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08009258B2

公开(公告)日：2011-08-30

申请号：US11773969

申请日：2007-07-06

Applicant: Yung-Chien Chen

Inventor： Yung-Chien Chen

IPC: G02F1/1345

CPC classification number: H01J29/92 ,  H01J17/02 ,  H01J2211/46 ,  H01J2329/92 ,  H05K1/0269 ,  H05K3/361 ,  H05K2201/09918 ,  H05K2203/163 ,  H05K2203/166

Abstract: A display panel including a substrate and a plurality of films for carrying chips is provided. The substrate has a display region and a non-display region located at one side of the display region. The non-display region has a plurality of pad regions, and each pad region has a plurality of first leads and at least one first displacement measuring mark disposed therein. The first displacement measuring mark is located at at least one side of all the first leads. The films for carrying chips are correspondingly sticking on the substrate. Each film for carrying chips has a plurality of second leads and at least one second displacement measuring mark. The second displacement measuring mark is located at least one side of all the second leads and is corresponding to the first displacement measuring mark. The second leads are correspondingly connected with the first leads.

Abstract translation: 提供一种显示面板，包括基板和多个用于承载芯片的薄膜。 基板具有位于显示区域一侧的显示区域和非显示区域。 非显示区域具有多个焊盘区域，并且每个焊盘区域具有多个第一引线和设置在其中的至少一个第一位移测量标记。 第一位移测量标记位于所有第一引线的至少一侧。 用于承载芯片的膜相应地粘附在基板上。 用于承载芯片的每个薄膜具有多个第二引线和至少一个第二移位测量标记。 第二位移测量标记位于所有第二引线的至少一侧，并且对应于第一位移测量标记。 第二引线相应地与第一引线连接。

公开(公告)号：US07995353B2

公开(公告)日：2011-08-09

申请号：US12189802

申请日：2008-08-12

Applicant: Chang-Te Liao

Inventor： Chang-Te Liao

IPC: H05K3/00 ,  H05K3/30 ,  H05K3/40

CPC classification number: H05K1/0269 ,  H05K1/111 ,  H05K3/303 ,  H05K3/3421 ,  H05K2201/09063 ,  H05K2201/09381 ,  H05K2201/09918 ,  H05K2203/166 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A circuit board includes four positioning pads placed on a surface of the circuit board, four positioning holes corresponding to the positioning pads, respectively, and a solder mask placed on the surface around the periphery of the positioning pads. An arc-shaped recess is defined at a side of each positioning pad near the corresponding positioning hole and the space between the edges of the positioning pad and the positioning hole ranges from 0.2 mm to 0.5 mm.

Abstract translation: 电路板包括放置在电路板的表面上的四个定位焊盘，分别对应于定位焊盘的四个定位孔和放置在定位焊盘周围表面上的焊接掩模。 在相应定位孔附近的每个定位垫的一侧限定有弧形凹部，并且定位垫和定位孔的边缘之间的间隔在0.2mm至0.5mm的范围内。

公开(公告)号：US20110169164A1

公开(公告)日：2011-07-14

申请号：US12968405

申请日：2010-12-15

Applicant: Junichi NAKAMURA ,  Kazuhiro Kobayashi

Inventor： Junichi NAKAMURA ,  Kazuhiro Kobayashi

IPC: H01L23/498 ,  H05K1/00 ,  H05K3/10

CPC classification number: H05K3/10 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81132 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/351 ,  H05K1/0269 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/025 ,  H05K2203/0361 ,  H05K2203/1152 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.

Abstract translation: 所公开的布线基板包括绝缘层，形成在绝缘层的表面上的凹部和形成在凹部内部的对准标记，其中对准标记的表面被粗糙化，从绝缘层的表面凹陷， 从凹槽露出。

公开(公告)号：US07969553B2

公开(公告)日：2011-06-28

申请号：US12187706

申请日：2008-08-07

Applicant: Jin Sato ,  Masaru Yamaga

Inventor： Jin Sato ,  Masaru Yamaga

IPC: G03B27/32 ,  G01B11/00

CPC classification number: G03F7/2002 ,  G03F9/708 ,  G03F9/7084 ,  G03F9/7088 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K1/0393 ,  H05K3/0008 ,  H05K3/0082 ,  H05K3/064 ,  H05K2201/09918 ,  H05K2203/0505 ,  H05K2203/0557 ,  H05K2203/056 ,  H05K2203/1545 ,  H01L2924/00

Abstract: The present invention relates to an exposure device for transferring circuit patterns of a mask to a roll-film-shaped object. The exposure device includes a supply reel rotation section that is constituted by a supply reel around which the object is wound and that feeds the object by rotating the supply reel, at least one guide roller for guiding the object fed from the supply reel rotation section, an exposure stage on which the circuit patterns are transferred to the object guided by the guide roller, and an alignment mark forming section which forms, on the object, alignment marks that are used to align the mask with the object and which is positioned between the guide roller and the exposure stage.

Abstract translation: 本发明涉及一种用于将掩模的电路图案转印到卷膜物体上的曝光装置。 曝光装置包括供给卷轴旋转部，该供给卷轴旋转部由卷绕物体的供给卷轴构成，并且通过旋转供给卷轴而进给物体;至少一个引导从供给卷轴旋转部送出的物体的引导辊， 电路图案被传送到由引导辊引导的物体的曝光阶段，以及对准标记形成部分，其在物体上形成用于将掩模与物体对准的对准标记，并且位于 导辊和曝光阶段。

公开(公告)号：US07945087B2

公开(公告)日：2011-05-17

申请号：US11768118

申请日：2007-06-25

Applicant: Zvi Kotler ,  Eliezer Lipman ,  Golan Hanina ,  Boris Greenberg ,  Michael Zenou

Inventor： Zvi Kotler ,  Eliezer Lipman ,  Golan Hanina ,  Boris Greenberg ,  Michael Zenou

IPC: G06K9/00

CPC classification number: G05B19/182 ,  G05B2219/45026 ,  G05B2219/49338 ,  G05B2219/49353 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/0035 ,  H05K2201/09918 ,  H05K2201/2054 ,  H05K2203/108

Abstract: A method for micromachining a material, including configuring an optical system to provide illumination of an illumination wavelength to a site via a given element of the optical system, the illumination generating returning radiation from the site. The method further includes configuring the optical system to receive the returning radiation via the given element, and to form an image of the site therefrom, calculating an actual position of a location at the site from the image and outputting a signal indicative of the actual position of the location, generating a beam of micromachining radiation having a micromachining wavelength different from the illumination wavelength, positioning the beam to form an aligned beam with respect to the location in response to the signal, and conveying the aligned beam to the location via at least the given element of the optical system so as to perform a micromachining operation at the location.

Abstract translation: 一种用于微加工材料的方法，包括配置光学系统以通过所述光学系统的给定元件向位置提供照明波长的照明，所述照明产生从所述现场返回的辐射。 该方法还包括配置光学系统以经由给定元件接收返回的辐射，并且从该图像形成站点的图像，从图像计算位置的位置的实际位置并输出指示实际位置的信号 产生具有不同于照明波长的微加工波长的微加工辐射束，定位该波束以响应于该信号而相对于该位置形成对准的波束，并且经由至少至少将该对准的波束传送到该位置 光学系统的给定元件，以便在该位置执行微加工操作。

公开(公告)号：US20110083323A1

公开(公告)日：2011-04-14

申请号：US12895824

申请日：2010-09-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/00

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/09918 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.

Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。