公开(公告)号：US08199519B2

公开(公告)日：2012-06-12

申请号：US12770768

申请日：2010-04-30

申请人： Ming-Chih Hsieh ,  Heng-Chen Kuo

发明人： Ming-Chih Hsieh ,  Heng-Chen Kuo

IPC分类号： H05K1/11 ,  H01L23/12

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/49805 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49153 ,  H01L2924/00

摘要： A chip adapter used to install a chip on a first chip arranging area of a circuit board includes a board. The size of the board has the same size as the first chip arranging area of the circuit board. Edges of the chip adapter define a number of gaps corresponding to first pads of the circuit board. A second chip arranging area of the same size as the chip is arranged in a center of the chip adapter. A number of second pads are arranged around the second chip arranging area of the chip adapter corresponding to pins of the chip. Each second pad is electrically connected to a sidewall of the corresponding gap of the chip adapter.

摘要翻译： 用于在电路板的第一芯片布置区域上安装芯片的芯片适配器包括板。 电路板的尺寸与电路板的第一芯片布置区域的尺寸相同。 芯片适配器的边缘限定了与电路板的第一焊盘相对应的多个间隙。 与芯片尺寸相同的第二芯片布置区域布置在芯片适配器的中心。 围绕芯片适配器的第二芯片布置区域布置多个第二焊盘，其对应于芯片的引脚。 每个第二焊盘电连接到芯片适配器的相应间隙的侧壁。

公开(公告)号：US20120037408A1

公开(公告)日：2012-02-16

申请号：US12987697

申请日：2011-01-10

申请人： Myung Whun CHANG ,  Dae Hyeong LEE ,  Ki Pyo HONG

发明人： Myung Whun CHANG ,  Dae Hyeong LEE ,  Ki Pyo HONG

IPC分类号： H05K1/09 ,  H05K1/00 ,  H01K3/10

CPC分类号： H05K1/11 ,  G01R1/02 ,  H05K1/09 ,  H05K3/225 ,  H05K3/4015 ,  H05K3/4061 ,  Y10T29/49002 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49726 ,  Y10T29/49748

摘要： There is provided a method of repairing a probe board, the method including: preparing a plurality of first via electrodes filled with a first filling material in a board body formed as a ceramic sintered body; forming a via hole for an open via electrode among the plurality of first via electrodes; filling the via hole with a second filling material having a lower sintering temperature than that of the first filling material; and forming a second via electrode by sintering the second filling material. The open via repair according to the present invention improves the manufacturing yield of the board and reduces the manufacturing costs thereof.

摘要翻译： 提供了一种修复探针板的方法，所述方法包括：在形成为陶瓷烧结体的板体中制备多个填充有第一填充材料的第一通孔电极; 在所述多个第一通孔电极中形成用于开放通孔电极的通孔; 用具有比第一填充材料低的烧结温度的第二填充材料填充通孔; 以及通过烧结所述第二填充材料形成第二通孔电极。 根据本发明的开放通孔修复提高了板的制造成品率并降低了其制造成本。

公开(公告)号：US20110278054A1

公开(公告)日：2011-11-17

申请号：US12780499

申请日：2010-05-14

申请人： I-Tseng Lee ,  Yi-Hsiu Liu ,  Jen-Yi Tsai

发明人： I-Tseng Lee ,  Yi-Hsiu Liu ,  Jen-Yi Tsai

IPC分类号： H05K1/16 ,  H05K3/34 ,  H05K1/00

CPC分类号： H05K3/3442 ,  H05K1/111 ,  H05K3/0005 ,  H05K2201/09381 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149

摘要： Various circuit board conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided. The method includes forming a first conductor pad on a circuit board. The first conductor pad includes a first notch and is adapted to couple to a first solder portion.

摘要翻译： 公开了各种电路板导体结构及其制造方法。 一方面，提供一种制造方法。 该方法包括在电路板上形成第一导体焊盘。 第一导体焊盘包括第一凹口并且适于耦合到第一焊料部分。

公开(公告)号：US08028403B2

公开(公告)日：2011-10-04

申请号：US12379156

申请日：2009-02-13

申请人： Deepak K. Pai ,  Ronald R. Denny

发明人： Deepak K. Pai ,  Ronald R. Denny

IPC分类号： H05K3/36 ,  B23K31/00

CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

摘要： The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

摘要翻译： 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

公开(公告)号：US08015703B2

公开(公告)日：2011-09-13

申请号：US12081835

申请日：2008-04-22

申请人： Hitoki Kanagawa ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

发明人： Hitoki Kanagawa ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

IPC分类号： H01R9/00 ,  H05K3/00

CPC分类号： H05K1/112 ,  G11B5/4833 ,  H01L2224/11003 ,  H01L2224/742 ,  H05K1/056 ,  H05K3/06 ,  H05K3/244 ,  H05K3/28 ,  H05K3/363 ,  H05K3/44 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/10666 ,  H05K2203/0323 ,  H05K2203/041 ,  H05K2203/0455 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

摘要： A method of manufacturing a wired circuit board including a metal supporting board. An insulating layer is formed on the metal supporting board in a pattern in which concave portions are formed. A conductive pattern in a pattern having terminals for connecting with external terminals via a molten metal is formed on the metal supporting board and the insulating layer. The terminals include shoulder portions corresponding to the concave portions and are concaved downward from an upper surface. First through holes penetrate the terminals in a thickness direction thereof Second through holes are formed communicating with the first through holes in portions of the insulating layer corresponding to the terminals by removing the concave portions to expose a lower surface of the terminals such that the second through holes penetrate the insulating layer in a thickness direction thereof and have a diameter larger than that of the first through holes.

摘要翻译： 一种制造包括金属支撑板的布线电路板的方法。 绝缘层以形成有凹部的图案形成在金属支撑板上。 在金属支撑板和绝缘层上形成具有用于经由熔融金属与外部端子连接的端子的图案中的导体图案。 端子包括对应于凹部的肩部，并且从上表面向下凹入。 第一通孔在厚度方向上贯穿端子。通过除去凹部以露出端子的下表面，在绝缘层的与端子对应的部分中的第一通孔形成第二通孔，以使第二通孔 孔的厚度方向穿过绝缘层，其直径大于第一通孔的直径。

公开(公告)号：US20110192646A1

公开(公告)日：2011-08-11

申请号：US12702455

申请日：2010-02-09

申请人： Kevin Allan Dooley ,  Joshua David Bell

发明人： Kevin Allan Dooley ,  Joshua David Bell

IPC分类号： H01R4/00 ,  H01R43/00

CPC分类号： H04R9/00 ,  H01R43/24 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49224

摘要： Matrices of multiple cast conductors, and methods for making such matrices. Methods according to the disclosure comprise: casting a conductor matrix including a plurality of conductors joined by at least one link; applying a surface treatment to at least a portion of the matrix; finishing a contact face on at least one of the conductors; and separating the conductors from each other at the at least one link.

摘要翻译： 多个铸造导体的矩阵，以及制造这种基体的方法。 根据本公开的方法包括：铸造包括由至少一个连杆连接的多个导体的导体矩阵; 对所述基质的至少一部分进行表面处理; 在至少一个导体上完成接触面; 以及在所述至少一个链节处彼此分离所述导体。

公开(公告)号：US20110175637A1

公开(公告)日：2011-07-21

申请号：US12998228

申请日：2009-09-29

申请人： Goro Nakatani ,  Masahiro Sakuragi ,  Koichi Niino

发明人： Goro Nakatani ,  Masahiro Sakuragi ,  Koichi Niino

IPC分类号： G01R31/00 ,  H05K3/00 ,  H01L21/02 ,  H05K13/04

CPC分类号： G01R1/07307 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/26 ,  H05K3/4084 ,  H05K2203/0195 ,  Y10T29/41 ,  Y10T29/49002 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165

摘要： Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

摘要翻译： 提供一种用于制造分批检查多个半导体器件的电特性的探针卡的方法。 该方法包括：在形成探针卡的基体的基板的一侧上形成与半导体器件的外部端子接触的多个探针的步骤; 通过光刻和蚀刻在板上形成从板的另一侧到达探针的多个通孔的步骤; 在通孔中分别形成与探针导电连接的电极的步骤; 以及在所述板的另一侧上形成与所述贯通电极导电连接的布线的步骤。

公开(公告)号：US07975379B2

公开(公告)日：2011-07-12

申请号：US12462985

申请日：2009-08-11

申请人： Gareth G. Hougham ,  Brian S. Beaman ,  John S. Corbin ,  Paul Coteus ,  Shawn A. Hall ,  Kathleen C. Hinge ,  Theron L. Lewis ,  Frank R. Libsch ,  Amanda E. E. Mikhail

发明人： Gareth G. Hougham ,  Brian S. Beaman ,  John S. Corbin ,  Paul Coteus ,  Shawn A. Hall ,  Kathleen C. Hinge ,  Theron L. Lewis ,  Frank R. Libsch ,  Amanda E. E. Mikhail

IPC分类号： H01R9/00

CPC分类号： H05K3/368 ,  H01R12/52 ,  H01R12/714 ,  H05K1/0269 ,  H05K3/325 ,  H05K2201/10378 ,  Y10T29/49117 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

摘要： LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating surfaces.

摘要翻译： LGA连接器采用预制到不同高度的按钮或弹簧触点制成，以适应特定产品类型的典型模块或PCB的初始形貌。 这是通过测量第一电子装置和第二电子装置的配合表面的形貌来制造的; 制造内插器触点以形成具有用于接触配合表面的相应反向形状的相对非平面侧; 并且将所述插入件夹在所述第一和第二电子设备之间，所述相对侧与相应的配合表面相接触。

公开(公告)号：US20110131805A1

公开(公告)日：2011-06-09

申请号：US12929726

申请日：2011-02-11

申请人： Shadi A. Abughazaleh ,  Joseph E. Dupuis ,  Christopher W. Gribble ,  Naved S. Khan ,  Douglas P. O'Connor

发明人： Shadi A. Abughazaleh ,  Joseph E. Dupuis ,  Christopher W. Gribble ,  Naved S. Khan ,  Douglas P. O'Connor

IPC分类号： H05K3/00

CPC分类号： H01R24/64 ,  H01R13/24 ,  H01R13/2442 ,  H01R13/405 ,  H01R13/6466 ,  H01R13/6625 ,  H01R13/6658 ,  H01R24/62 ,  H01R43/20 ,  H01R43/205 ,  H01R2107/00 ,  H05K1/18 ,  H05K1/182 ,  H05K3/325 ,  H05K3/4015 ,  H05K2201/0133 ,  H05K2201/0311 ,  H05K2201/1031 ,  H05K2201/10424 ,  H05K2201/10446 ,  Y02P70/611 ,  Y10S439/941 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151

摘要： An electrical connector adapted to receive a mating plug utilizes low-profile jack terminal contacts that can flex in their PCB-anchored base portions, which are substantially parallel to the PCB. Any bend in the distal connecting portion or in the intermediate transition portion of each terminal contact is gradual and forms an obtuse angle, thus minimizing stress concentrations. The contacts preferably are arranged in two oppositely facing and interdigitating rows of four contacts each. In one embodiment, the terminal contacts are anchored to the PCB by a contact cradle that constrains the base portion of each terminal contact at two spaced anchoring locations, allowing the base portion to flex therebetween. In another embodiment, the base portions of the terminal contacts are embedded in at least one elastomeric member, which is fitted to the PCB.

摘要翻译： 适于接收配合插头的电连接器利用能够在其PCB固定的基座部分上弯曲的低轮廓的插座端子触头，其基本上平行于PCB。 每个末端接触件的远端连接部分或中间过渡部分中的任何弯曲是渐进的并且形成钝角，从而最小化应力集中。 触点优选地布置在两个相互面对的和交叉的四行触点中。 在一个实施例中，端子触头通过接触支架锚固到PCB，该接触支架将两个间隔开的锚固位置限制每个端子触头的基部，从而允许基部在其间弯曲。 在另一个实施例中，端子触点的基部嵌入至少一个弹性体构件中，该弹性构件安装到PCB上。

公开(公告)号：US07937828B2

公开(公告)日：2011-05-10

申请号：US11509684

申请日：2006-08-25

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H05K3/20

CPC分类号： H05K1/186 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/82 ,  H01L2224/83001 ,  H01L2224/85 ,  H01L2224/86 ,  H01L2924/00013 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/53174 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wiring board including an insulating layer where a semiconductor chip is embedded includes: forming, on a supporting board, the insulating layer where the semiconductor chip is embedded and a wiring connected to the semiconductor chip; removing the supporting board by etching; and simultaneously forming first and second reinforcing layers so as to sandwich the insulating layer after removing the supporting board.

摘要翻译： 制造包括半导体芯片的绝缘层的布线板的制造方法包括：在支撑基板上形成嵌入半导体芯片的绝缘层和与半导体芯片连接的布线; 通过蚀刻去除支撑板; 同时形成第一和第二增强层，以便在去除支撑板之后夹住绝缘层。