公开(公告)号：US12020756B2

公开(公告)日：2024-06-25

申请号：US18134719

申请日：2023-04-14

申请人： Kioxia Corporation

发明人： Noboru Shibata ,  Hironori Uchikawa ,  Taira Shibuya

IPC分类号： G11C16/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  H10B69/00

CPC分类号： G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459 ,  H10B69/00

摘要： A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US20240096798A1

公开(公告)日：2024-03-21

申请号：US18389582

申请日：2023-11-14

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B10/00 ,  H10B12/00 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B10/125 ,  H10B12/37 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L2225/06541

摘要： A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US11923339B2

公开(公告)日：2024-03-05

申请号：US17318186

申请日：2021-05-12

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Jun Liu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H10B10/00 ,  H10B12/00 ,  H10B69/00

CPC分类号： H01L25/0657 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/32146 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H10B10/00 ,  H10B12/00 ,  H10B69/00

摘要： Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.

公开(公告)号：US11908526B2

公开(公告)日：2024-02-20

申请号：US17589365

申请日：2022-01-31

申请人： Kioxia Corporation

发明人： Naoto Kumano ,  Kenji Sakurada

IPC分类号： G11C16/26 ,  G11C16/04 ,  G06F11/10 ,  H10B69/00

CPC分类号： G11C16/26 ,  G06F11/1004 ,  G11C16/0483 ,  H10B69/00

摘要： According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

公开(公告)号：US11901287B2

公开(公告)日：2024-02-13

申请号：US17476344

申请日：2021-09-15

申请人： Micron Technology, Inc.

发明人： Shuangqiang Luo ,  Lifang Xu

IPC分类号： H01L23/522 ,  H01L21/768 ,  H10B69/00

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H10B69/00

摘要： Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

公开(公告)号：US20230397447A1

公开(公告)日：2023-12-07

申请号：US18235995

申请日：2023-08-21

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786

CPC分类号： H10B99/00 ,  H01L27/1207 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1225 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/7869 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/78693 ,  H01L29/78696 ,  G11C2211/4016 ,  H01L21/8221

摘要： An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US11839084B2

公开(公告)日：2023-12-05

申请号：US17825619

申请日：2022-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC分类号： H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/28 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/522 ,  H10B41/50 ,  H10B43/50 ,  H10B69/00 ,  H01L29/66 ,  H10B43/30

CPC分类号： H10B43/27 ,  H01L21/28525 ,  H01L21/76868 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/66833 ,  H10B41/50 ,  H10B43/30 ,  H10B43/50 ,  H10B69/00

摘要： A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US11832453B2

公开(公告)日：2023-11-28

申请号：US17678429

申请日：2022-02-23

申请人： KIOXIA CORPORATION

发明人： Kosei Noda

IPC分类号： H01L21/768 ,  H10B69/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/311

CPC分类号： H10B69/00 ,  H01L21/76877 ,  H01L21/31111 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53295

摘要： According to one embodiment, a semiconductor storage device includes a stacked body above a substrate. The stacked body includes a first stacked region in which a first insulating layer and a second insulating layer are alternately stacked and a second stacked region in which a conductive layer and the first insulating layer are alternately stacked. The semiconductor storage device includes a memory pillar that extends through the second stacked region of the stacked body in a stacking direction. The second insulating layer comprising a first insulating material within the first stacked region and a second insulating material on ends of the second insulating layer in a direction intersecting to the stacking direction.

公开(公告)号：US20230371286A1

公开(公告)日：2023-11-16

申请号：US18225186

申请日：2023-07-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC分类号： H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC分类号： H10B69/00 ,  H01L29/7869 ,  H01L27/0688 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US11818878B2

公开(公告)日：2023-11-14

申请号：US17868722

申请日：2022-07-19

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： G11C5/06 ,  H10B12/00 ,  H01L21/265 ,  G11C16/04 ,  H01L27/088 ,  H01L29/66 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L29/78 ,  H01L23/528 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/10

CPC分类号： H10B12/20 ,  G11C5/063 ,  G11C11/4096 ,  G11C11/4099 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/26586 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/785 ,  H01L29/7841 ,  H10B12/50 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  G11C2211/4016

摘要： NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.