公开(公告)号：US20110183447A1

公开(公告)日：2011-07-28

申请号：US13014108

申请日：2011-01-26

Applicant: Jong-joo LEE

Inventor： Jong-joo LEE

IPC: H01L21/66 ,  H01L21/50

CPC classification number: H01L21/6835 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.

Abstract translation: 制造堆叠半导体封装的方法，其中堆叠多个半导体芯片包括制备包括第一半导体器件，第一穿透电极和第一连接单元的第一半导体芯片，该第一半导体芯片电连接到第一半导体器件或第一穿透 电极，将第一半导体芯片与第一连接单元插入到基底基板之间，通过使用打印方法在第一半导体芯片上形成第一重新布线图案和第一保护层，其中第一重新布线图案电连接到 第一穿透电极和第一保护层部分地覆盖第一重新布线图案并暴露第一重新布线图案的其他部分，并且将包括第二半导体器件的第二半导体芯片附接到第一半导体芯片以将第二半导体器件电连接到第一 重新布线图案

公开(公告)号：US07964948B2

公开(公告)日：2011-06-21

申请号：US11790359

申请日：2007-04-25

Applicant: Jong-joo Lee ,  Sun-won Kang

Inventor： Jong-joo Lee ,  Sun-won Kang

IPC: H01L23/02

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.

Abstract translation: 芯片堆叠可以包括堆叠在第一芯片上的第一芯片和第二芯片。 第一和第二芯片中的每一个可以包括具有活性表面和与活性表面相对的非活性表面的基底; 活动表面内部电路; 有源表面上的I / O芯片焊盘，并通过I / O缓冲器连接到内部电路; 以及通过I / O缓冲器通过电路布线连接到I / O芯片焊盘的I / O连接焊盘。 再分布的I / O芯片焊盘层可以在第一芯片的有源表面上，重新分布的I / O芯片焊盘层重新分布I / O芯片焊盘。 第一芯片和第二芯片的I / O连接焊盘可以通过电连接部分彼此电连接。

公开(公告)号：US20100090326A1

公开(公告)日：2010-04-15

申请号：US12588382

申请日：2009-10-14

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

Abstract translation: 堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。 第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。 第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。 电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口电连接到第一半导体芯片的通孔，与焊盘间隔开的外连接焊盘和 连接配线，从连接焊盘的开口延伸到外部连接焊盘。

公开(公告)号：US20080289177A1

公开(公告)日：2008-11-27

申请号：US12126364

申请日：2008-05-23

Applicant: Jong-Joo Lee ,  Soon-Yong Hur

Inventor： Jong-Joo Lee ,  Soon-Yong Hur

IPC: H05K3/02

CPC classification number: H05K3/242 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/064 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Provided are a circuit board, a semiconductor package including the circuit board, a method of fabricating the circuit board, and a method of fabricating the semiconductor package. The method of fabricating the circuit board includes: forming at least one pair of rows of first bonding pads arranged on a base substrate in a first direction, and a first central plating line formed between the rows of first bonding pads to commonly connect with the rows of first bonding pads; forming an electroplating layer on the first bonding pads; and exposing the base substrate by removing the first central plating line.

Abstract translation: 提供了一种电路板，包括电路板的半导体封装，制造电路板的方法以及制造半导体封装的方法。 制造电路板的方法包括：在第一方向上形成布置在基底基板上的至少一对第一接合焊盘列，以及形成在第一接合焊盘行之间的第一中心电镀线，以与行共同连接 的第一粘接垫; 在所述第一接合焊盘上形成电镀层; 并且通过去除第一中心电镀线来暴露基底。

公开(公告)号：US20080211081A1

公开(公告)日：2008-09-04

申请号：US11951024

申请日：2007-12-05

Applicant: Jong-Joo LEE

Inventor： Jong-Joo LEE

IPC: H01L23/48

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.

Abstract translation: 提供一种平面多半导体芯片封装，其中处理器和存储器件经由通孔彼此连接，以及制造平面多芯片封装的方法。 平面多晶半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 包括布置在所述基板上的多个存储器件的第一半导体芯片，其中第一存储器件围绕第二存储器件的至少一部分; 堆叠在第一半导体芯片上并对应于第二存储器件的第二半导体芯片; 以及布置在第二存储器件上并将第一和第二半导体芯片连接到基板的第二电路图案的多个贯通电极。

公开(公告)号：US20070170575A1

公开(公告)日：2007-07-26

申请号：US11627791

申请日：2007-01-26

Applicant: Jong-Joo LEE ,  Dong-Ho LEE

Inventor： Jong-Joo LEE ,  Dong-Ho LEE

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

公开(公告)号：US07131847B2

公开(公告)日：2006-11-07

申请号：US11001182

申请日：2004-12-02

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H01R13/2485 ,  G01R1/0466 ,  G01R1/0491 ,  H01R2201/20

Abstract: A test apparatus may include a test socket having socket pins with a standard configuration. An intermediate connection board may be interposed between the test socket and a package that has solder balls with a non-standard configuration. The intermediate connection board may have contact balls and contact pads. The contact balls may be arranged in a configuration that is compatible with the standard socket pin configuration, and the contact pads may be arranged in a configuration that is compatible with the non-standard solder ball configuration.

Abstract translation: 测试装置可以包括具有标准配置的插座引脚的测试插座。 中间连接板可以插入在测试插座和具有非标准配置的焊球的封装之间。 中间连接板可以具有接触球和接触垫。 接触球可以布置成与标准插座销配置兼容的配置，并且接触焊盘可以布置成与非标准焊球配置兼容的配置。

公开(公告)号：US20060220215A1

公开(公告)日：2006-10-05

申请号：US11378899

申请日：2006-03-17

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/52

CPC classification number: H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

Abstract: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

公开(公告)号：US20050260868A1

公开(公告)日：2005-11-24

申请号：US11001182

申请日：2004-12-02

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L21/66 ,  H01R12/00 ,  H01R13/24

CPC classification number: H01R13/2485 ,  G01R1/0466 ,  G01R1/0491 ,  H01R2201/20

Abstract: A test apparatus may include a test socket having socket pins with a standard configuration. An intermediate connection board may be interposed between the test socket and a package that has solder balls with a non-standard configuration. The intermediate connection board may have contact balls and contact pads. The contact balls may be arranged in a configuration that is compatible with the standard socket pin configuration, and the contact pads may be arranged in a configuration that is compatible with the non-standard solder ball configuration.

Abstract translation: 测试装置可以包括具有标准配置的插座引脚的测试插座。 中间连接板可以插入在测试插座和具有非标准配置的焊球的封装之间。 中间连接板可以具有接触球和接触垫。 接触球可以布置成与标准插座销配置兼容的配置，并且接触焊盘可以布置成与非标准焊球配置兼容的配置。

公开(公告)号：US08796847B2

公开(公告)日：2014-08-05

申请号：US13198738

申请日：2011-08-05

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/498 ,  H01L23/48 ,  H05K3/34 ,  H05K1/11 ,  H01L25/065 ,  H01L23/00 ,  H05K1/02 ,  H01L23/31

CPC classification number: H05K1/111 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/06154 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17517 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09781 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package substrate includes an insulating substrate, a functional pattern and a main dummy pattern. A semiconductor chip is arranged on the insulating substrate. The functional pattern is formed on the insulating substrate. The functional pattern is electrically connected to the semiconductor chip. The main dummy pattern is formed on a portion of the insulating substrate at least of to the outside of and/or adjacent the functional pattern in a path of stress generated by a difference between thermal expansion coefficient of the insulating substrate and the semiconductor chip, so as to divert the stress away from the functional pattern. Thus, the stress is not concentrated on the functional pattern. As a result, damage to the functional bump caused by the stress is prevented.

Abstract translation: 封装基板包括绝缘基板，功能图案和主虚拟图案。 半导体芯片布置在绝缘基板上。 功能图案形成在绝缘基板上。 功能图案电连接到半导体芯片。 主绝缘基板的绝缘基板的至少一部分在由绝缘基板和半导体芯片的热膨胀系数之差产生的应力路径中至少在功能图案的外侧和/或相邻的部分上形成，因此， 将压力从功能模式转移出去。 因此，应力不集中在功能图案上。 结果，防止了由应力引起的功能性凸起的损坏。