公开(公告)号：US08900924B2

公开(公告)日：2014-12-02

申请号：US14173340

申请日：2014-02-05

Applicant: Xintec Inc.

Inventor： Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L25/00 ,  H01L21/822 ,  B81C1/00 ,  H01L21/768 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在第一芯片上的第二芯片; 从所述第一芯片的表面向所述第二芯片延伸的孔; 导电层，设置在所述第一芯片的表面上并延伸到所述孔中并电连接到所述第一芯片中的导电区域或掺杂区域; 以及设置在所述第一芯片和所述第二芯片之间的支撑体，其中所述支撑体基本上和/或完全覆盖所述孔的底部。

公开(公告)号：US20140319670A1

公开(公告)日：2014-10-30

申请号：US14325812

申请日：2014-07-08

Applicant: XINTEC INC.

Inventor： Wen-Cheng CHIEN ,  Wen-Ken HUANG ,  Chien-Hung LIU ,  Joey LAI

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/05 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/02235 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad;and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：衬底，其上具有半导体器件和导电焊盘; 填充形成在所述衬底中的沟槽的绝缘体环，其中所述绝缘体环围绕所述导电焊盘下方的中间层; 以及设置在所述基板的背面下方并与导电焊盘电连接的导电层。

公开(公告)号：US20140264785A1

公开(公告)日：2014-09-18

申请号：US14207224

申请日：2014-03-12

Applicant: XINTEC INC.

Inventor： Yi-Min LIN ,  Yi-Ming CHANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US20140252642A1

公开(公告)日：2014-09-11

申请号：US14198542

申请日：2014-03-05

Applicant: XINTEC INC.

Inventor： Bai-Yao LOU ,  Shih-Kuang CHEN ,  Sheng-Yuan LEE

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L23/48 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：半导体衬底; 形成在所述半导体衬底中的器件区域; 至少一个设置在所述半导体衬底的表面上的导电焊盘; 设置在所述半导体衬底的表面上的保护板; 以及设置在所述半导体衬底的表面和所述保护板之间的间隔层，其中所述保护板和所述间隔层围绕所述器件区域的空腔，所述间隔层具有远离所述腔的外侧表面，并且所述外侧 间隔层的表面不是切割面。

公开(公告)号：US20140213010A1

公开(公告)日：2014-07-31

申请号：US14166749

申请日：2014-01-28

Applicant: Xintec Inc.

Inventor： Chih-Hao CHEN ,  Bai-Yao LOU ,  Shih-Kuang CHEN

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L21/2007 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid.

Abstract translation: 晶片封装方法包括以下步骤。 提供透光载体。 在透光性载体上形成水解性临时粘接层。 透光性保护片的第一表面与水解性临时粘合层接合，使得水解临时粘合层位于透光保护片和透光性载体之间。 透光保护片的背离第一表面的第二表面被结合到晶片的第三表面。 透光载体，水解临时粘合层，透光保护片和晶片浸入高温液体中，从而消除了水解临时粘合层的粘附力。 透光保护片和晶片是从高温液体中获得的。

公开(公告)号：US20140203416A1

公开(公告)日：2014-07-24

申请号：US14225336

申请日：2014-03-25

Applicant: XINTEC INC.

Inventor： Yu-Ting HUANG

IPC: H01L23/552 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/482 ,  H01L23/552 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer.

Abstract translation: 芯片封装包括：基板; 信号焊盘和设置在所述基板上的接地焊盘; 第一导电层和第二导电层，其分别设置在所述基板上并电连接到所述信号焊盘和所述接地焊盘，其中所述第一和第二导电层沿着所述第一和第二导电层从所述基板的上表面延伸到所述基板的下表面 第一和第二侧面分别与第一和第二导电层从下表面突出; 以及设置在所述基板上的保护层，其中所述保护层完全覆盖位于所述基板的所述第一侧表面上的所述第一导电层的整个部分，并且所述第二导电层的位于所述基板的第二侧表面上的整个部分 衬底不被保护层覆盖。

公开(公告)号：US20130307161A1

公开(公告)日：2013-11-21

申请号：US13895219

申请日：2013-05-15

Applicant: Xintec Inc.

Inventor： Shu-Ming CHANG ,  Yu-Ting HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/538 ,  H01L21/78

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US20130307147A1

公开(公告)日：2013-11-21

申请号：US13895235

申请日：2013-05-15

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L23/49811 ,  B81B7/0061 ,  B81B7/0067 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L27/14618 ,  H01L33/486 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a chip package including: a substrate having a first surface and a second surface; a device region located in the substrate; a conducting pad structure disposed on the substrate and electrically connected to the device region; a spacer layer disposed on the first surface of the substrate; a second substrate disposed on the spacer layer, wherein a cavity is created and surrounded by the second substrate, the spacer layer, and the substrate on the device region; and a through-hole extending from a surface of the second substrate towards the substrate, wherein the through-hole connects to the cavity.

Abstract translation: 本发明的实施例提供一种芯片封装，包括：具有第一表面和第二表面的基板; 位于所述基板中的器件区域; 导电焊盘结构，设置在所述基板上并电连接到所述器件区域; 设置在所述基板的第一表面上的间隔层; 设置在所述间隔层上的第二衬底，其中由所述第二衬底，所述间隔层和所述器件区域上的衬底产生并包围空腔; 以及从所述第二基板的表面朝向所述基板延伸的通孔，其中所述通孔连接到所述空腔。

公开(公告)号：US20130207240A1

公开(公告)日：2013-08-15

申请号：US13829802

申请日：2013-03-14

Applicant: XINTEC INC.

Inventor： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一个实施例提供一种芯片封装结构。

公开(公告)号：US20130154077A1

公开(公告)日：2013-06-20

申请号：US13720649

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Kuo-Hua LIU ,  Yi-Ming CHANG ,  Hsi-Chien LIN

IPC: H01L21/78 ,  H01L23/48

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/48 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract translation: 芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。