公开(公告)号：US09865466B2

公开(公告)日：2018-01-09

申请号：US15240410

申请日：2016-08-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Ellie Y. Yieh ,  Mehul B. Naik ,  Srinivas D. Nemani

IPC: H01L21/44 ,  H01L21/285 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/28518 ,  C23C16/42 ,  C23C16/4418 ,  C23C16/511 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/28556 ,  H01L21/324 ,  H01L21/76864 ,  H01L21/76885 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271

Abstract: Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.

公开(公告)号：US09777378B2

公开(公告)日：2017-10-03

申请号：US14635589

申请日：2015-03-02

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Erica Chen ,  Ludovic Godet ,  Jun Xue ,  Ellie Y. Yieh

IPC: C23C16/56 ,  C23C16/32 ,  C23C14/48 ,  C23C16/40 ,  C23C16/04

CPC classification number: C23C16/56 ,  C23C16/045 ,  C23C16/401

Abstract: Embodiments described herein relate to methods for forming flowable chemical vapor deposition (FCVD) films suitable for high aspect ratio gap fill applications. Various process flows described include ion implantation processes utilized to treat a deposited FCVD film to improve dielectric film density and material composition. Ion implantation processes, curing processes, and annealing processes may be utilized in various sequence combinations to form dielectric films having improved densities at temperatures within the thermal budget of device materials. Improved film quality characteristics include reduced film stress and reduced film shrinkage when compared to conventional FCVD film formation processes.

公开(公告)号：US09748148B2

公开(公告)日：2017-08-29

申请号：US14736020

申请日：2015-06-10

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. Yieh ,  Huixiong Dai ,  Srinivas D. Nemani ,  Ludovic Godet ,  Christopher Dennis Bencher

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/20

Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.

公开(公告)号：US09595467B2

公开(公告)日：2017-03-14

申请号：US14597149

申请日：2015-01-14

Applicant: Applied Materials, Inc.

Inventor： Jun Xue ,  Ludovic Godet ,  Erica Chen ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/786 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/223 ,  H01J37/32 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32412 ,  H01J37/32422 ,  H01L21/2236 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/768 ,  H01L21/76825 ,  H01L23/5222

Abstract: Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.

Abstract translation: 提供了使用离子注入工艺形成在互连结构的不同位置上形成的所需材料的互连结构中的空气间隙以限定蚀刻边界，然后进行半导体器件的蚀刻工艺的方法。 在一个实施例中，一种用于在衬底上形成互连结构中的气隙的方法，所述方法包括将离子注入设置在衬底上的绝缘材料的第一区域中，留下没有注入离子的第二区域，第二区域具有第一 与第一区域接合的表面和与衬底接合的第二表面，以及执行蚀刻工艺以选择性地蚀刻第二区域远离衬底，在第一区域和衬底之间形成气隙。

公开(公告)号：US20160307768A1

公开(公告)日：2016-10-20

申请号：US15194456

申请日：2016-06-27

Applicant: Applied Materials, Inc.

Inventor： Hao CHEN ,  Chentsau (Chris) Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/306 ,  H01L21/3065 ,  C23C16/50 ,  H01L21/3213 ,  H01L21/67 ,  C23C16/04 ,  C23C16/455 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/3086 ,  C23C16/04 ,  C23C16/34 ,  C23C16/345 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J37/32082 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/67742

Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

Abstract translation: 多周期间隔物的第一部分形成在衬底上的图案化特征的侧壁上。 使用第一等离子体工艺在第一部分上沉积间隔层。 使用第二等离子体工艺蚀刻间隔层以在第一部分上形成多循环间隔物的第二部分。 连续重复包括沉积和蚀刻间隔层的循环，直到形成多循环间隔物。

公开(公告)号：US11798606B2

公开(公告)日：2023-10-24

申请号：US17328491

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US11764058B2

公开(公告)日：2023-09-19

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H10B12/00

CPC classification number: H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/02579 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/30

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US11682556B2

公开(公告)日：2023-06-20

申请号：US17672305

申请日：2022-02-15

Applicant: Applied Materials, Inc.

Inventor： Jie Zhou ,  Erica Chen ,  Qiwei Liang ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/26

CPC classification number: H01L21/02527 ,  C23C16/02 ,  C23C16/26 ,  H01L21/0262 ,  H01L21/02425 ,  H01L21/02488

Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

公开(公告)号：US11631591B2

公开(公告)日：2023-04-18

申请号：US17408943

申请日：2021-08-23

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. Citla ,  Jethro Tannos ,  Jingyi Li ,  Douglas A. Buchberger, Jr. ,  Zhong Qiang Hua ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: C23C16/505 ,  H01L21/311 ,  H01L21/762 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/67 ,  C23C16/515 ,  H01L21/02 ,  C23C16/509 ,  C23C16/517

Abstract: Methods for depositing a dielectric material using RF bias pulses along with remote plasma source deposition for manufacturing semiconductor devices, particularly for filling openings with high aspect ratios in semiconductor applications are provided. For example, a method of depositing a dielectric material includes providing a gas mixture into a processing chamber having a substrate disposed therein, forming a remote plasma in a remote plasma source and delivering the remote plasma to an interior processing region defined in the processing chamber, applying a RF bias power to the processing chamber in pulsed mode, and forming a dielectric material in an opening defined in a material layer disposed on the substrate in the presence of the gas mixture and the remote plasma.

公开(公告)号：US20230066497A1

公开(公告)日：2023-03-02

申请号：US17978447

申请日：2022-11-01

Applicant: Applied Materials, Inc.

Inventor： Mei-Yee Shek ,  Bhargav S. Citla ,  Joshua Rubnitz ,  Jethro Tannos ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: C23C16/36 ,  C01B21/082 ,  C23C16/44 ,  C23C16/50 ,  C09D1/00

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.