公开(公告)号：US20060000639A1

公开(公告)日：2006-01-05

申请号：US10882170

申请日：2004-07-02

申请人： John Lauffer ,  James Larnerd ,  Voya Markovich

发明人： John Lauffer ,  James Larnerd ,  Voya Markovich

IPC分类号： H05K1/11

CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4641 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.

摘要翻译： 电路化衬底，其包括沿其至少一个导电层的侧边缘部分的多个邻接的开放段，这些开放段通过电介质材料的屏障隔离，所述阻挡层基本上填充开放段，例如在层压过程期间 将基板的两个电介质层粘合到导电层。 还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

公开(公告)号：US20050250249A1

公开(公告)日：2005-11-10

申请号：US11182167

申请日：2005-07-15

申请人： Lisa Jimarez ,  Miguel Jimarez ,  Voya Markovich ,  Cynthia Milkovich ,  Charles Perry ,  Brenda Peterson

发明人： Lisa Jimarez ,  Miguel Jimarez ,  Voya Markovich ,  Cynthia Milkovich ,  Charles Perry ,  Brenda Peterson

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46

CPC分类号： H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

摘要： An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

摘要翻译： 提供电子封装和制造电子封装的方法。 电介质材料层位于包括多个导电触点的衬底的第一表面上。 至少一个通孔形成在电介质材料层中，与多个导电触点中的至少一个对准。 导电材料位于基本上填充通孔的至少一个通孔中。 至少一个导电构件定位在通孔中的导电材料上并与导电材料电接触。 该电子封装提高了组件的现场使用寿命，该组件包括附接到衬底的第二表面的半导体芯片和附着到导电构件的印刷线路板。

公开(公告)号：US20050023035A1

公开(公告)日：2005-02-03

申请号：US10933260

申请日：2004-09-03

申请人： James Fuller ,  John Lauffer ,  Voya Markovich

发明人： James Fuller ,  John Lauffer ,  Voya Markovich

IPC分类号： H05K3/32 ,  H05K3/46 ,  H05K1/11

CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

摘要： An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

公开(公告)号：US20050011670A1

公开(公告)日：2005-01-20

申请号：US10915483

申请日：2004-08-11

申请人： James Fuller ,  John Lauffer ,  Voya Markovich

发明人： James Fuller ,  John Lauffer ,  Voya Markovich

IPC分类号： H05K3/32 ,  H05K3/46 ,  H05K1/03

CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

摘要： A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

摘要翻译： 电路化基板组件及其制造方法，其中所述组件包括结合在一起的各个电路化基板。 基板各自包括至少一个开口，其中仅一个开口在接合之前基本上填充有导电浆料。 一旦粘合，糊料也部分地位于另一个开口内，以提供与其的有效电连接。

公开(公告)号：US20050005439A1

公开(公告)日：2005-01-13

申请号：US10912257

申请日：2004-08-05

申请人： Karen Carpenter ,  Voya Markovich ,  David Thomas

发明人： Karen Carpenter ,  Voya Markovich ,  David Thomas

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01K3/10 ,  H05K1/03 ,  H05K1/16 ,  H05K3/30

CPC分类号： H05K1/115 ,  H05K1/0268 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/162 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： An electrical structure, and associated method of formation, that includes a complex power-signal (CPS) substructure. The CPS substructure is formed and tested to determine whether the CPS substructure satisfies electrical performance acceptance requirements. The testing includes testing for electrical shorts, electrical opens, erroneous impedances, and electrical signal delay. If the CPS substructure passes the tests, then a dielectric-metallic (DM) laminate is formed on an external surface of the CPS substructure. The DM laminate includes an alternating sequence of an equal number N of dielectric layers and metallic layers such that a first dielectric layer of the N dielectric layers is formed on an external surface of the CPS substructure. N is at least 2. A multilevel conductive via is formed through the DM laminate and is electrically coupled to a metal layer of the CPS substructure.

摘要翻译： 电气结构和相关的形成方法，其包括复合功率信号（CPS）子结构。 形成和测试CPS子结构以确定CPS子结构是否满足电气性能验收要求。 测试包括测试电气短路，电气开路，错误阻抗和电信号延迟。 如果CPS子结构通过测试，则在CPS子结构的外表面上形成介电金属（DM）层压体。 DM层压板包括相等数量的N个介电层和金属层的交替序列，使得N个介电层的第一介电层形成在CPS子结构的外表面上。 N至少为2.通过DM层压体形成多层导电通孔，并电耦合到CPS子结构的金属层。

公开(公告)号：US4786528A

公开(公告)日：1988-11-22

申请号：US864978

申请日：1986-05-20

申请人： William J. Amelio ,  Voya Markovich ,  William J. McCarthy ,  Allen F. Moring ,  Peter A. Moschak ,  Douglas H. Strope

发明人： William J. Amelio ,  Voya Markovich ,  William J. McCarthy ,  Allen F. Moring ,  Peter A. Moschak ,  Douglas H. Strope

IPC分类号： C08J5/24 ,  B29B13/02 ,  B29B13/06 ,  B29B15/08 ,  B29C70/06 ,  B29C71/00 ,  B29K63/00 ,  B29K105/06 ,  B29L9/00 ,  H05K1/03 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46 ,  B05D3/02 ,  B05D3/12

CPC分类号： H05K3/0011 ,  B29C71/00 ,  B29C2793/0045 ,  B29C2793/009 ,  B29L2031/3425 ,  H05K1/0366 ,  H05K2203/1105 ,  H05K3/0047 ,  H05K3/0082

摘要： Reinforced synthetic polymer composite is treated by heating at a temperature and for a time sufficient to obtain a moisture content below that for the relative humidity level at which the composite is to be drilled and/or photoresist exposed; and then subjecting it to conditions to increase the moisture content to that for the relative humidity level of the drilling.

摘要翻译： 加强合成聚合物复合材料通过在足以获得低于复合材料被钻孔和/或光刻胶曝光的相对湿度水平的温度和时间下加热处理; 然后使其处于条件以将水分含量增加到钻井的相对湿度水平。

公开(公告)号：US4654126A

公开(公告)日：1987-03-31

申请号：US785128

申请日：1985-10-07

申请人： William J. Amelio ,  Voya Markovich ,  Carlos J. Sambucetti ,  Donna J. Trevitt

发明人： William J. Amelio ,  Voya Markovich ,  Carlos J. Sambucetti ,  Donna J. Trevitt

IPC分类号： C23C18/31 ,  C23C18/16 ,  G01N27/26 ,  G01N27/48 ,  G01N27/46

CPC分类号： C23C18/1683 ,  C23C18/405 ,  C23C18/32 ,  C23C18/42

摘要： A process for monitoring an electroless plating bath to determine whether it is in a take mode by electrolessly depositing a film of the metal of the plating bath onto a substrate to provide a preplated cathode; providing the cathode, a reference electrode, and an anode in the electroless bath; passing an electric current and varying the voltage difference, plotting the voltage difference versus the current; and comparing the oxidation peak of the reducing agent to the oxidation peak of the reduced state of the metal ion to be plated to thereby determine whether the bath is in a take mode.

摘要翻译： 一种用于监测化学镀浴以通过将电镀浴的金属膜无电沉积到衬底上以确定其是否处于取样模式以提供预镀阴极的方法; 在无电镀浴中提供阴极，参比电极和阳极; 传递电流并改变电压差，绘制电压差与电流; 并将还原剂的氧化峰与待镀金属离子的还原态的氧化峰进行比较，从而确定浴是否处于取样模式。

公开(公告)号：US4534797A

公开(公告)日：1985-08-13

申请号：US567723

申请日：1984-01-03

申请人： David E. King ,  Voya Markovich ,  Carlos J. Sambucetti ,  Stephen L. Tisdale ,  Donna J. Trevitt

发明人： David E. King ,  Voya Markovich ,  Carlos J. Sambucetti ,  Stephen L. Tisdale ,  Donna J. Trevitt

IPC分类号： H05K3/18 ,  C23C18/40 ,  C23C3/02

CPC分类号： C23C18/40

摘要： An electroless copper plating bath which is in the take mode is provided by determining the amount in the bath of at least four of the components selected from the group of oxygen, reducing agent, cyanide salt, cupric salt, and complexing agent; solving the equation:R=(CABD)/Ewherin C is the concentration of cupric salt, A is the concentration of reducing agent, B is the concentration of oxygen, D is the concentration of cyanide salt, E is the concentration of complexing agent, and R is a unitless number.The bath is provided with quantities of the above ingredients so that R in the equation is between about 5 and about 15.

摘要翻译： 通过确定浴中至少四种选自氧，还原剂，氰化物盐，铜盐和络合剂的组分中的量来提供处于取样模式的化学镀铜浴; 求解方程：R =（CABD）/ E，C是铜盐的浓度，A是还原剂的浓度，B是氧的浓度，D是氰化物盐的浓度，E是络合剂的浓度 ，R是无单位数。 浴中提供了上述成分的数量，使得方程式中的R为约5至约15。

公开(公告)号：US4525390A

公开(公告)日：1985-06-25

申请号：US588035

申请日：1984-03-09

申请人： Warren A. Alpaugh ,  William J. Amelio ,  Voya Markovich ,  Carlos J. Sambucetti

发明人： Warren A. Alpaugh ,  William J. Amelio ,  Voya Markovich ,  Carlos J. Sambucetti

IPC分类号： C23C18/40 ,  C23C18/52 ,  H05K3/18 ,  C23C3/02

CPC分类号： H05K3/181 ,  C23C18/40

摘要： Copper is deposited onto a substrate by plating a first layer of copper onto the substrate from an electroless plating bath and plating a second layer of copper onto the first layer of copper from a second and different electroless plating bath. The first and second plating baths differ from each other in at least the cyanide content and oxygen content. The process reduces plating void defects and reduces nodule formation.

摘要翻译： 通过从无电解镀浴将铜的第一层镀到衬底上并将铜从第二和不同的化学镀浴镀到第一层铜上，从而将铜沉积到衬底上。 至少氰化物含量和氧含量，第一和第二电镀槽彼此不同。 该方法减少电镀空隙缺陷并减少结节形成。

公开(公告)号：US20080105457A1

公开(公告)日：2008-05-08

申请号：US12007178

申请日：2008-01-08

申请人： Frank Egitto ,  Voya Markovich ,  Luis Matienzo

发明人： Frank Egitto ,  Voya Markovich ,  Luis Matienzo

IPC分类号： H05K1/03

CPC分类号： H05K3/462 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/015 ,  H05K2201/0245 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T156/1056 ,  Y10T156/1062

摘要： A circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.

摘要翻译： 一种电路化基板，包括与低温导电浆料组合的高温电介质材料，所述糊料包括有机粘合剂成分和至少一种金属成分。 当电介质用作衬底中的层时，金属部件的薄片被烧结以形成通过电介质的导电路径。