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118 条记录 (耗时 0.039 秒)

    Virtually substrate-less composite power semiconductor device and method
    61.
    发明授权
    Virtually substrate-less composite power semiconductor device and method 有权
    几乎无衬底复合功率半导体器件及方法

    公开(公告)号：US08242013B2

    公开(公告)日：2012-08-14

    申请号：US12749696

    申请日：2010-03-30

    申请人： Tao Feng ,  Yueh-Se Ho

    发明人： Tao Feng ,  Yueh-Se Ho

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/561 ,  H01L23/142 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/92 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.

    摘要翻译： 公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。 载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘 。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。 厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

    Method of forming ultra thin chips of power devices
    65.
    发明申请
    Method of forming ultra thin chips of power devices 审中-公开
    形成功率器件超薄芯片的方法

    公开(公告)号：US20080242052A1

    公开(公告)日：2008-10-02

    申请号：US11694888

    申请日：2007-03-30

    申请人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

    发明人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

    IPC分类号： H01L21/30

    CPC分类号： H01L21/3043 ,  H01L21/78

    摘要： A method for making thin semiconductor devices is disclosed. Starting from wafer with pre-fabricated front-side devices, the method includes: Thinning wafer central portion from its back-side to produce a thin region while preserving original wafer thickness in the wafer periphery for structural strength. Forming ohmic contact at wafer back-side. Separating and collecting pre-fabricated devices. This further includes: Releasably bonding wafer back-side onto single-sided dicing tape, in turn supported by a dicing frame. Providing a backing plate to match the thinned out wafer central portion. Sandwiching the dicing tape between wafer and backing plate then pressing the dicing tape to bond with the wafer. With a step-profiled chuck to support wafer back-side, the pre-fabricated devices are separated from each other and from the wafer periphery in one dicing operation with dicing depth slightly thicker than the wafer central portion. The separated thin semiconductor devices are then picked up and collected.

    摘要翻译： 公开了制造薄半导体器件的方法。 从具有预制的前端器件的晶片开始，该方法包括：从其背面将晶片中心部分变薄以产生薄区域，同时在晶片周边保留原始晶片厚度以获得结构强度。 在晶圆背面形成欧姆接触。 分离和收集预制设备。 这还包括：将晶片背面可释放地粘合到单面切割胶带上，然后由切割架支撑。 提供背板以匹配变薄的晶片中心部分。 将切割胶带夹在晶片和背板之间，然后按压切割胶带与晶片结合。 利用阶梯型卡盘来支撑晶片背面，在一个切割操作中，预制的装置彼此分离并且与晶片周边分离，切割深度比晶片中心部分稍厚。 然后拾取并收集分离的薄半导体器件。

    Chip scale surface mount package for semiconductor device and process of fabricating the same
    69.
    发明授权
    Chip scale surface mount package for semiconductor device and process of fabricating the same 有权

    公开(公告)号：US06441475B2

    公开(公告)日：2002-08-27

    申请号：US09733823

    申请日：2000-12-08

    申请人： Felix Zandman ,  Y. Mohammed Kasem ,  Yueh-Se Ho

    发明人： Felix Zandman ,  Y. Mohammed Kasem ,  Yueh-Se Ho

    IPC分类号： H01L2302

    CPC分类号： H01L25/50 ,  H01L23/49805 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

    摘要： This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. The resulting package thus includes a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate. The package is essentially the same size as the die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.

    Process of fabricating a chip scale surface mount package for semiconductor device
    70.
    发明授权
    Process of fabricating a chip scale surface mount package for semiconductor device 有权

    公开(公告)号：US06271060B1

    公开(公告)日：2001-08-07

    申请号：US09395095

    申请日：1999-09-13

    申请人： Felix Zandman ,  Y. Mohammed Kasem ,  Yueh-Se Ho

    发明人： Felix Zandman ,  Y. Mohammed Kasem ,  Yueh-Se Ho

    IPC分类号： H01L2144

    CPC分类号： H01L25/50 ,  H01L23/49805 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

    摘要： This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. The resulting package thus includes a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate. The package is essentially the same size as the die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.