公开(公告)号：US06610591B1

公开(公告)日：2003-08-26

申请号：US09645833

申请日：2000-08-25

Applicant: Tongbi Jiang ,  Salman Akram

Inventor： Tongbi Jiang ,  Salman Akram

IPC: H01L2144

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10234 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A ball grid array for a flip chip assembly. The ball grid array including a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow. Therefore, when bonding the semiconductor device to the substrate, the ball grid array provides sufficient electrical and mechanical connection despite any non-planarity in the active surface of the semiconductor device and the top surface of the substrate, and any differing height in the plurality of balls due to testing the semiconductor device.

Abstract translation: 用于倒装芯片组件的球栅阵列。 该球栅阵列包括多个凸起，该多个凸块接合在半导体管芯的有源表面和印刷电路板的顶表面之间或任何类型的衬底载体上。 多个球包括至少一个具有芯材料和外层的凸块。 芯材的刚性大于外层材料的刚性。 此外，芯材料的熔化温度高于外层的材料。 通过这种布置，具有外层的芯材料提供高度基本均匀的凸块。 此外，在老化测试和回流过程中，球只会对芯材料产生痕迹或变形。 因此，当将半导体器件接合到衬底时，尽管在半导体器件的有源表面和衬底的顶表面中存在任何非平坦性，但球栅阵列提供足够的电和机械连接，并且多个 由于测试了半导体器件。

公开(公告)号：US20030119299A1

公开(公告)日：2003-06-26

申请号：US10358810

申请日：2003-02-05

Inventor： Tongbi Jiang ,  Salman Akram

IPC: H01L021/48 ,  H01L021/44 ,  H01L021/50

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10234 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A ball grid array for a flip-chip assembly. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow. Therefore, when bonding the semiconductor device to the substrate, the ball grid array provides sufficient electrical and mechanical connection despite any non-planarity in the active surface of the semiconductor device and the top surface of the substrate, and any differing height in the plurality of balls due to testing the semiconductor device.

Abstract translation: 用于倒装芯片组合的球栅阵列。 球栅阵列包括结合在半导体管芯的有源表面和印刷电路板的顶表面之间的多个凸起或任何类型的衬底载体。 多个球包括至少一个具有芯材料和外层的凸块。 芯材的刚性大于外层材料的刚性。 此外，芯材料的熔化温度高于外层的材料。 通过这种布置，具有外层的芯材料提供高度基本均匀的凸块。 此外，在老化测试和回流过程中，球只会对芯材料产生痕迹或变形。 因此，当将半导体器件接合到衬底时，尽管在半导体器件的有源表面和衬底的顶表面中存在任何非平坦性，但球栅阵列提供足够的电和机械连接，并且多个 由于测试了半导体器件。

公开(公告)号：US20030091800A1

公开(公告)日：2003-05-15

申请号：US10035975

申请日：2001-11-09

Applicant: Polyclad Laminates, Inc.

Inventor： Dong Zhang

IPC: B32B003/00

CPC classification number: C08J5/24 ,  H05K1/0366 ,  H05K1/0373 ,  H05K2201/012 ,  H05K2201/0212 ,  Y10T428/24917 ,  Y10T428/249999 ,  Y10T428/253 ,  Y10T428/2933 ,  Y10T442/209 ,  Y10T442/2139 ,  Y10T442/259 ,  Y10T442/2631

Abstract: The present invention is directed to filled prepregs, laminates, printed circuit boards comprising a reinforcing material impregnated with a cured polymeric resin, the cured polymeric resin comprising multicellular polymeric microspheres as a filler. Pre-pregs, laminates and printed circuit boards prepared by this method have reduced dielectric constant as low as 3.0, depending upon the resin system of the matrix. In addition, such laminates and printed circuit boards have enhanced electrical, thermal and mechanical properties as well as improved machinability, low density and a uniform appearance.

Abstract translation: 本发明涉及填充的预浸料，层压板，印刷电路板，其包含浸渍有固化的聚合物树脂的增强材料，所述固化的聚合物树脂包含多细胞聚合物微球体作为填料。 通过该方法制备的预浸料，层压板和印刷电路板根据基体的树脂体系将介电常数降低到3.0。 此外，这种层压板和印刷电路板具有增强的电，热和机械性能以及改善的机械加工性，低密度和均匀的外观。

公开(公告)号：US20030067313A1

公开(公告)日：2003-04-10

申请号：US10014886

申请日：2001-12-14

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Toshiyuki Toyoshima ,  Suguru Nagae

IPC: G01R031/02

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/0212 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic device assembled using a coupler which has an electroconductive region and a resin region on the surface. Flexibility of the resin region absorbs stress caused by difference in thermal expansion coefficient between an organic printed circuit board and a semiconductor chip through the deformation of the electroconductive region. As a result, formation of cracking in the coupler is avoided. It is preferable that the resin region occupies from 20 to 80% of the total surface area of the coupler. The coupler may be formed from a molten blend of the heat resistant resin and a joining metal. The coupler may also be formed by molding a blend of the heat resistant resin and metal powder, wherein the metal powder locating on the surface of the coupler have a joining metal joined thereto.

Abstract translation: 使用在表面具有导电区域和树脂区域的耦合器组装的电子设备。 树脂区域的柔软性通过导电区域的变形吸收由有机印刷电路板和半导体芯片之间的热膨胀系数的差异引起的应力。 结果，避免了在耦合器中形成裂纹。 树脂区域优选占耦合器总表面积的20〜80％。 耦合器可以由耐热树脂和接合金属的熔融共混物形成。 耦合器还可以通过模制耐热树脂和金属粉末的共混物而形成，其中定位在耦合器表面上的金属粉末具有与其接合的接合金属。

公开(公告)号：US06528145B1

公开(公告)日：2003-03-04

申请号：US09606359

申请日：2000-06-29

Applicant: Daniel George Berger ,  Shaji Farooq ,  Lester Wynn Herron ,  James N. Humenik ,  John Ulrich Knickerbocker ,  Robert William Pasco ,  Charles H. Perry ,  Krishna G. Sachdev

Inventor： Daniel George Berger ,  Shaji Farooq ,  Lester Wynn Herron ,  James N. Humenik ,  John Ulrich Knickerbocker ,  Robert William Pasco ,  Charles H. Perry ,  Krishna G. Sachdev

IPC: G02B600

CPC classification number: H05K1/0373 ,  H01L21/4857 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/4611 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/24479 ,  Y10T428/24917 ,  Y10T428/24942 ,  Y10T428/249955 ,  Y10T428/249956 ,  Y10T428/251 ,  Y10T428/254 ,  Y10T428/259 ,  H01L2924/00

Abstract: A composite electronic and/or optical substrate including polymeric and ceramic material wherein the composite substrate has a dielectric constant less than 4 and a coefficient of thermal expansion of 8 to 14 ppm/°C. at 100° C. The composite substrate may be either ceramic-filled polymeric material or polymer-filled ceramic material.

Abstract translation: 包括聚合物和陶瓷材料的复合电子和/或光学基底，其中复合基底具有小于4的介电常数和8-14ppm /℃的热膨胀系数。 在100℃下。复合衬底可以是陶瓷填充的聚合材料或聚合物填充的陶瓷材料。

公开(公告)号：US06514560B2

公开(公告)日：2003-02-04

申请号：US10068878

申请日：2002-02-11

Applicant: Kyung wook Paik ,  Myung jin Yim ,  Woon seong Kwon

Inventor： Kyung wook Paik ,  Myung jin Yim ,  Woon seong Kwon

IPC: B05D510

CPC classification number: H01L24/83 ,  C08L63/00 ,  C09J7/10 ,  C09J9/02 ,  C09J2201/602 ,  C09J2463/00 ,  H01L24/28 ,  H01L2224/2919 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H05K3/323 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0239 ,  H05K2201/10674 ,  H05K2203/0783 ,  H01L2924/00

Abstract: Disclosed is a method for manufacturing a low dielectric constant conductive adhesive that is appropriate for a radio frequency packaging application. This method is characterized by mixing a thermosetting resin with surface-treated conductive particles and non-conductive particles for prevention of agglutination and thereby forming the conductive adhesive. The manufactured conductive adhesive is useful for a bonding material of the radio frequency packaging. According to the present invention, it is possible to obtain a flip chip bonding having superior mechanical and electrical performance compared with the conventional flip chip bonding art. Also, since the adhesive has a low high frequency loss and a low dielectric constant, it is possible to realize a flip chip package having a superior electrical performance. The conductive adhesive is particularly useful for the flip chip packaging of a device having a bandwidth of microwave and millimeter wave.

Abstract translation: 公开了适用于射频封装应用的低介电常数导电粘合剂的制造方法。 该方法的特征在于将热固性树脂与表面处理的导电颗粒和非导电颗粒混合以防止凝集，从而形成导电粘合剂。 所制造的导电粘合剂可用于射频包装的接合材料。 根据本发明，与传统的倒装芯片接合技术相比，可以获得具有优异的机械和电气性能的倒装芯片接合。 此外，由于粘合剂具有低的高频损耗和低介电常数，所以可以实现具有优异的电性能的倒装芯片封装。 导电粘合剂对于具有微波和毫米波带宽的器件的倒装芯片封装特别有用。

公开(公告)号：US20030017414A1

公开(公告)日：2003-01-23

申请号：US10158159

申请日：2002-05-31

Inventor： Kenji Ishii ,  Nobuyuki Ikeguchi ,  Takabumi Omori ,  Daisuke Ohno

IPC: G03F007/027

CPC classification number: G03F7/038 ,  G03F7/027 ,  H05K3/287 ,  H05K2201/0212

Abstract: A photosensitive resin composition (C) containing a photosensitive resin (B) which is a reaction product produced by modifying an epoxy acrylate (a) with a cyanate ester compound (b) to obtain a modification product (A) and reacting the modification product (A) with a polybasic acid anhydride (c), and a compound (d) of the formula, 1 in which each of n and m is an integer of at least 1, and a cured product of the photosensitive resin composition (C).

Abstract translation: 一种含有感光性树脂（B）的感光性树脂组合物（B），该感光性树脂（B）是通过用氰酸酯化合物（b）改性环氧丙烯酸酯（a）而得到的反应产物，得到改性产物（A） A）和n为1以上的整数的多元酸酐（c）和下式化合物（d）和感光性树脂组合物（C）的固化物。

公开(公告)号：US20030008133A1

公开(公告)日：2003-01-09

申请号：US10185002

申请日：2002-07-01

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Kyung wook Paik ,  Myung jin Yim

IPC: B05D005/12 ,  B05D003/02

CPC classification number: H01B1/22 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/323 ,  H05K2201/0212 ,  H05K2201/0239 ,  H05K2201/10674 ,  Y10T428/26 ,  H01L2224/2919 ,  H01L2924/00 ,  H01L2224/16225

Abstract: Disclosed are an anisotropic conductive film and a method of fabricating the same suitable for realizing an ultra-fine pitch COG (Chip On Glass) application. The anisotropic conductive film of the present invention is characterized in that 1-30% by volume nonconductive particles (polymer, ceramic, etc.) having a diameter {fraction (1/20)}-null times as large as the conductive particles are added. According to the present invention, the anisotropic conductive film can prevent an electrical shorting between the bumps in bonding ultra fine pitch flip chip as well as in COG-bonding the driver IC. Accordingly, the anisotropic conductive film can be widely used in a communication field using ACA flip chip technology and universal flip chip packages.

Abstract translation: 公开了一种各向异性导电膜及其制造方法，其适用于实现超细间距COG（Glass On Glass）应用。 本发明的各向异性导电膜的特征在于，添加1〜30体积％的导电性粒子（聚合物，陶瓷等），其直径为导电粒子的1 / 20-1 / 5倍。 根据本发明，各向异性导电膜可以防止在结合超细间距倒装芯片时的凸起之间的电短路以及COG接合驱动器IC中的电短路。 因此，各向异性导电膜可以广泛用于使用ACA倒装芯片技术和通用倒装芯片封装的通信领域。

公开(公告)号：US20030007332A1

公开(公告)日：2003-01-09

申请号：US09539864

申请日：2000-03-31

Inventor： Yasuaki Seki ,  Takashi Ito ,  Shuji Mochizuki ,  Kiyonori Furuta ,  Toshihiko Hatajima

IPC: H05K001/00

CPC classification number: H05K3/4644 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2203/095 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Herein is disclosed an insulating resin composition for a multilayer printed-wiring board, comprising two or more kinds of resins which are different in etching rate by plasma treatment and which are not compatible with each other, so that the surface of the resulting insulating layer can be made uneven by the plasma treatment, whereby the bonding strength of the conductor layer to the said resulting insulating layer can be ensured, and heat resistance and electrically insulating properties required can be satisfied.

公开(公告)号：US06465082B1

公开(公告)日：2002-10-15

申请号：US09554502

申请日：2000-05-16

Applicant: Hiroaki Takezawa ,  Masahide Tsukamoto ,  Minehiro Itagaki ,  Yoshihiro Bessho ,  Hideo Hatanaka ,  Yasushi Fukumura ,  Kazuo Eda ,  Toru Ishida

Inventor： Hiroaki Takezawa ,  Masahide Tsukamoto ,  Minehiro Itagaki ,  Yoshihiro Bessho ,  Hideo Hatanaka ,  Yasushi Fukumura ,  Kazuo Eda ,  Toru Ishida

IPC: H05K100

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K3/105 ,  H05K3/321 ,  H05K2201/0212 ,  H05K2201/0379 ,  H05K2201/10257 ,  H05K2201/10992 ,  H05K2203/121 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/254 ,  Y10T428/31681

Abstract: A stress relaxation type electronic component which is to be mounted on a circuit board, wherein a stress relaxation mechanism member is disposed on a surface of said electronic component, said surface being on a side of a connection portion where said electronic component is to be connected to said circuit board, and said stress relaxation mechanism member is electrically conductive.

Abstract translation: 一种要安装在电路板上的应力松弛型电子部件，其中应力松弛机构部件设置在所述电子部件的表面上，所述表面位于要连接所述电子部件的连接部分的一侧 到所述电路板，并且所述应力松弛机构构件是导电的。