公开(公告)号：US20080230923A1

公开(公告)日：2008-09-25

申请号：US12051619

申请日：2008-03-19

Applicant: Cha-Jea JO ,  Myung-Kee CHUNG ,  Nam-Seog KIM ,  In-Young LEE ,  Seok-Ho KIM ,  Ho-Jin LEE ,  Ju-Il CHOI ,  Chang-Woo SHIN

Inventor： Cha-Jea JO ,  Myung-Kee CHUNG ,  Nam-Seog KIM ,  In-Young LEE ,  Seok-Ho KIM ,  Ho-Jin LEE ,  Ju-Il CHOI ,  Chang-Woo SHIN

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20080128888A1

公开(公告)日：2008-06-05

申请号：US11895187

申请日：2007-08-23

Applicant: Myeong-soon Park ,  In-young Lee ,  Ho-jin Lee ,  Moon-sun Seo

Inventor： Myeong-soon Park ,  In-young Lee ,  Ho-jin Lee ,  Moon-sun Seo

IPC: H01L23/488 ,  H01L21/58

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: Provided is a system-in-package (SiP) including a main chip and one or more sub chips. In the SiP, a first surface of the main chip is electrically connected with a second surface of the main chip, through a via electrode, the one or more sub chips are assembled on the second surface of the main chip on which a ReDistribution Line (RDL) is formed, and the length of the SiP is substantially equal to the length of the main chip.

Abstract translation: 提供了包括主芯片和一个或多个子芯片的系统级封装（SiP）。 在SiP中，主芯片的第一表面通过通孔电极与主芯片的第二表面电连接，一个或多个子芯片组装在主芯片的第二表面上，在其上分布有再分布线 RDL），并且SiP的长度基本上等于主芯片的长度。

公开(公告)号：US07312143B2

公开(公告)日：2007-12-25

申请号：US11717691

申请日：2007-03-14

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Abstract translation: 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20070205512A1

公开(公告)日：2007-09-06

申请号：US11785980

申请日：2007-04-23

Applicant: In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

Inventor： In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract translation: 焊料凸块结构可以具有形成在半导体芯片的芯片焊盘上的金属螺柱。 金属螺柱的表面可以镀有焊料。 金属螺柱可以位于衬底的衬底焊盘上。 衬底垫可以具有施加到其上的预焊料。 在焊料回流之后，焊料凸点可以具有凹形。

公开(公告)号：US20070170556A1

公开(公告)日：2007-07-26

申请号：US11635011

申请日：2006-12-07

Applicant: Hyun-Soo Chung ,  Dong-Hyeon Jang ,  In-Young Lee ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  In-Young Lee ,  Dong-Ho Lee

IPC: H01L23/495

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/062 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/09745 ,  H05K2203/1184 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.

Abstract translation: 半导体器件可以包括半导体元件。 可以在半导体元件上提供一层材料，该层可以具有可以暴露接合焊盘的开口。 可以在第一接合焊盘上提供至少一个凸缘结构，所述至少一个凸缘结构由具有不同蚀刻速率的至少两个金属层制成。

公开(公告)号：US20060214293A1

公开(公告)日：2006-09-28

申请号：US11186763

申请日：2005-07-22

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Abstract translation: 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20060073704A1

公开(公告)日：2006-04-06

申请号：US11210817

申请日：2005-08-25

Applicant: Se-young Jeong ,  In-young Lee ,  Sung-min Sim ,  Young-hee Song ,  Dong-hyeon Jang ,  Myeong-soon Park ,  Sun-young Park ,  Sun-bum Kim ,  Hyun-soo Chung

Inventor： Se-young Jeong ,  In-young Lee ,  Sung-min Sim ,  Young-hee Song ,  Dong-hyeon Jang ,  Myeong-soon Park ,  Sun-young Park ,  Sun-bum Kim ,  Hyun-soo Chung

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: A method of forming a bump may involve providing a seed layer on a contact pad of a wafer. A shielding layer and a photosensitive mask layer may be formed on the seed layer. The photosensitive mask layer may be exposed and developed to form a mask pattern. An exposed portion of the shielding layer may be removed. The bump may be formed by plating the exposed seed layer.

Abstract translation: 形成凸块的方法可以包括在晶片的接触焊盘上提供种子层。 可以在种子层上形成屏蔽层和感光掩模层。 感光掩模层可以被曝光和显影以形成掩模图案。 可以去除屏蔽层的暴露部分。 可以通过电镀暴露的种子层来形成凸块。