公开(公告)号：US20050127508A1

公开(公告)日：2005-06-16

申请号：US10897124

申请日：2004-07-23

Applicant: In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

Inventor： In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract translation: 焊料凸块结构可以具有形成在半导体芯片的芯片焊盘上的金属螺柱。 金属螺柱的表面可以镀有焊料。 金属螺柱可以位于衬底的衬底焊盘上。 衬底垫可以具有施加到其上的预焊料。 在焊料回流之后，焊料凸点可以具有凹形。

公开(公告)号：US20070205512A1

公开(公告)日：2007-09-06

申请号：US11785980

申请日：2007-04-23

Applicant: In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

Inventor： In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract translation: 焊料凸块结构可以具有形成在半导体芯片的芯片焊盘上的金属螺柱。 金属螺柱的表面可以镀有焊料。 金属螺柱可以位于衬底的衬底焊盘上。 衬底垫可以具有施加到其上的预焊料。 在焊料回流之后，焊料凸点可以具有凹形。

公开(公告)号：US20050104222A1

公开(公告)日：2005-05-19

申请号：US10944613

申请日：2004-09-20

Applicant: Se-Young Jeong ,  Gu-Sung Kim ,  Nam-Seog Kim ,  Gi-Hwan Park ,  Se-Yong Oh ,  Soon-Bum Kim ,  In-Young Lee

Inventor： Se-Young Jeong ,  Gu-Sung Kim ,  Nam-Seog Kim ,  Gi-Hwan Park ,  Se-Yong Oh ,  Soon-Bum Kim ,  In-Young Lee

IPC: H01L23/28 ,  H01L21/60 ,  H01L23/16 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06102 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29076 ,  H01L2224/30155 ,  H01L2224/30156 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/013

Abstract: A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and electrically connected to the chip pads. And a solder bar may be provided on a portion of the protective layer. The solder bar may disperse thermal stress produced in the solder bumps. A metal core may be embedded within the solder bar. The flip chip device may be mounted on and flip-chip bonded to a substrate. The substrate may have land pads to which the solder bumps and the solder bar may be mechanically joined. The solder bar increases a joint area between the flip chip device and the substrate and reinforces solder connections therebetween.

Abstract translation: 倒装芯片器件可以具有其上可以设置有芯片焊盘和保护层的有源表面的半导体芯片。 可以在活性表面上提供焊料凸块并电连接到芯片焊盘。 并且可以在保护层的一部分上设置焊料条。 焊料棒可能会分散焊料凸点产生的热应力。 金属芯可以嵌入在焊条内。 倒装芯片器件可以安装在衬底上并倒装芯片结合到衬底上。 衬底可以具有焊盘，焊盘和焊条可以焊接到其上。 焊条增加了倒装芯片器件和衬底之间的接合面积，并加强了它们之间的焊接连接。

公开(公告)号：US07300864B2

公开(公告)日：2007-11-27

申请号：US10911672

申请日：2004-08-05

Applicant: Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

Inventor： Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

IPC: H01L21/44

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

Abstract translation: 可以使用可以是正性光致抗蚀剂的光致抗蚀剂的双曝光技术来形成焊料凸块结构。 正光致抗蚀剂可以涂覆在IC芯片上。 可以通过第一曝光工艺在光致抗蚀剂的第一曝光区域处形成第一开口。 金属突起可以形成在第一开口中。 可以通过第二曝光工艺在光致抗蚀剂的第二曝光区域处形成第二开口。 第二曝光区域可以包括由第一曝光工艺限定的非曝光区域。 焊料材料可以填充第二开口并且可以回流以形成焊料凸块。 金属突起可以嵌入在焊料凸块内。

公开(公告)号：US20050090089A1

公开(公告)日：2005-04-28

申请号：US10911672

申请日：2004-08-05

Applicant: Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

Inventor： Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

IPC: H01L21/60 ,  H01L21/44 ,  H01L23/485 ,  H01L23/50

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

Abstract translation: 可以使用可以是正性光致抗蚀剂的光致抗蚀剂的双曝光技术来形成焊料凸块结构。 正光致抗蚀剂可以涂覆在IC芯片上。 可以通过第一曝光工艺在光致抗蚀剂的第一曝光区域处形成第一开口。 金属突起可以形成在第一开口中。 可以通过第二曝光工艺在光致抗蚀剂的第二曝光区域处形成第二开口。 第二曝光区域可以包括由第一曝光工艺限定的非曝光区域。 焊料材料可以填充第二开口并且可以回流以形成焊料凸块。 金属突起可以嵌入在焊料凸块内。

公开(公告)号：US07786594B2

公开(公告)日：2010-08-31

申请号：US11822630

申请日：2007-07-09

Applicant: Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

Inventor： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.

Abstract translation: 一种晶片级堆叠结构，包括包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，第二晶片包括至少一个 第二芯片尺寸小于第一芯片尺寸的第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片尺寸，其中所述第一晶片 并且第二晶片被堆叠，并且其中第一晶片和第二晶片彼此耦合。 一种系统级封装，包括晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的至少一个第一器件芯片和至少一个具有第二多个I / O焊盘的第二器件芯片 ，以及与晶片级堆叠结构连接的公共电路板。

公开(公告)号：US20050205968A1

公开(公告)日：2005-09-22

申请号：US11131253

申请日：2005-05-16

Applicant: Gu-Sung Kim

Inventor： Gu-Sung Kim

IPC: H01L23/12 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/10 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3114 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/9201

Abstract: A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.

公开(公告)号：US06518675B2

公开(公告)日：2003-02-11

申请号：US09752856

申请日：2000-12-29

Applicant: Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

Inventor： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

Abstract: A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure, and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The thermal-stress-absorbing interface structure includes means for allowing the first end of the pad to move up when the second end of the pad moves down and alternately allowing the first end to move down when the second end moves up, upon thermal cycling. The means has a center axis and the up-and-down movements of the pad are balanced on the center axis. In accordance with this novel structure of the present invention, interconnection reliability such as solder joint reliability can be significantly improved.

Abstract translation: 半导体集成电路芯片和表面安装结构之间的热应力吸收界面结构及其制造方法。 热应力吸收界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块焊盘。 所述热应力吸收界面结构包括当所述垫的第二端向下移动时允许所述垫的第一端向上移动的装置，并且当热循环时，当所述第二端向上移动时交替允许所述第一端向下移动。 该装置具有中心轴线，并且该垫的上下移动在中心轴线上平衡。 根据本发明的这种新型结构，可以显着提高诸如焊点可靠性之类的互连可靠性。

公开(公告)号：US20100193903A1

公开(公告)日：2010-08-05

申请号：US12671280

申请日：2008-07-30

Applicant: Gu-Sung Kim

Inventor： Gu-Sung Kim

IPC: H01L23/525 ,  H01L21/50 ,  H01L21/768

CPC classification number: H01L23/5258 ,  H01L23/5382 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective.

Abstract translation: 提供一种三维半导体器件。 三维半导体器件包括其中堆叠多个半导体芯片或封装的主体，被配置为保护主体的外层芯片或封装并被配置为透射激光束的保护基板，以及具有 保险丝功能的形式，当至少一个芯片或封装有缺陷时，形成为通过穿透保护基板的激光束切断有缺陷的芯片或封装的电连接。

公开(公告)号：US07537959B2

公开(公告)日：2009-05-26

申请号：US11889400

申请日：2007-08-13

Applicant: Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

Inventor： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC: H01L21/00 ,  H01L21/26 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Abstract translation: 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。