公开(公告)号：US20100244277A1

公开(公告)日：2010-09-30

申请号：US12411154

申请日：2009-03-25

申请人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

发明人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/52

CPC分类号： H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.

摘要翻译： 一种制造集成电路封装系统的方法包括：提供具有堆叠互连器的牺牲载体组件; 将具有连接器的集成电路安装在所述牺牲载体组件上，所述连接器穿过所述堆叠互连器; 在牺牲载体组件和集成电路之间将底部填充材料分配到基本上没有空隙的底部填充材料; 将集成电路封装在牺牲载体组件和底部填充材料上; 通过去除牺牲载体组件暴露堆叠互连器; 并在底部填充材料和堆叠互连器之上形成基底阵列。

公开(公告)号：US20100244216A1

公开(公告)日：2010-09-30

申请号：US12410312

申请日：2009-03-24

申请人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

发明人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L25/065 ,  H01L21/50

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

摘要： A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.

摘要翻译： 通过在第一牺牲载体上形成导电层制成半导体器件。 在导电层上形成焊料凸块。 在第一载体，导电层和焊料凸块上沉积无流动的底部填充材料。 将半导体管芯或部件压缩成无流动底部填充材料以与导电层电接触。 无流动底部填充材料和第一焊料凸块的表面被平坦化。 第一互连结构形成在无流动底部填充材料的第一表面上。 第一互连结构电连接到焊料凸块。 第二牺牲载体安装在第一互连结构上。 第二互连结构形成在无流动底部填充材料的第二侧上。 第二互连结构电连接到第一焊料凸块。 半导体器件可以通过焊料凸块堆叠和电连接。

公开(公告)号：US20100140759A1

公开(公告)日：2010-06-10

申请号：US12332277

申请日：2008-12-10

申请人： Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

发明人： Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

IPC分类号： H01L23/552 ,  H01L21/00

CPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device is made by forming a build-up interconnect structure over a substrate. A semiconductor die is mounted to the build-up interconnect structure. The semiconductor die is electrically connected to the build-up interconnect structure. A ground pad is formed on the build-up interconnect structure. An encapsulant is formed over the semiconductor die and build-up interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the build-up interconnect structure to isolate the semiconductor die from inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. The substrate is removed. A backside interconnect structure is formed over the build-up interconnect structure, opposite the semiconductor die.

摘要翻译： 通过在衬底上形成积聚互连结构来制造半导体器件。 半导体管芯安装到堆积互连结构。 半导体管芯与积层互连结构电连接。 在积层互连结构上形成接地焊盘。 在半导体管芯和堆积互连结构之上形成密封剂。 在形成密封剂之前，可以在半导体管芯上方形成屏蔽笼。 在形成积层互连结构之后，在密封剂上形成屏蔽层，以将半导体管芯与器件间干扰隔离。 屏蔽层符合密封剂的几何形状并且电连接到接地垫。 屏蔽层可以通过导电柱电连接到地面。 去除衬底。 在积层互连结构上形成背面互连结构，与半导体管芯相对。

公开(公告)号：US07732252B2

公开(公告)日：2010-06-08

申请号：US12248878

申请日：2008-10-09

申请人： Seng Guan Chow ,  Heap Hoe Kuan ,  Rui Huang

发明人： Seng Guan Chow ,  Heap Hoe Kuan ,  Rui Huang

IPC分类号： H01L21/44 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a multi-chip package system that includes: providing a package substrate; attaching a base semiconductor die to the package substrate; connecting an interconnect between the base semiconductor die and the package substrate; and encapsulating at least portions of the package substrate, the base semiconductor die, and the interconnect with an encapsulant defining a support protrusion adjacent to the interconnect and substantially perpendicular to the package substrate, a cavity bounded by the support protrusion, and a gap linking the cavity to the edge of the encapsulant.

摘要翻译： 本发明提供一种多芯片封装系统，其包括：提供封装基板; 将基底半导体管芯附接到封装衬底; 连接所述基底半导体管芯和所述封装衬底之间的互连; 并且将封装衬底，基底半导体管芯和互连件的至少一部分封装在与所述互连件相邻并且基本上垂直于所述封装衬底的限定支撑突起的密封剂上，由所述支撑突起限定的空腔以及将 空腔到密封剂的边缘。

公开(公告)号：US20100123251A1

公开(公告)日：2010-05-20

申请号：US12273547

申请日：2008-11-19

申请人： Seng Guan Chow ,  Heap Hoe Kuan ,  Rui Huang

发明人： Seng Guan Chow ,  Heap Hoe Kuan ,  Rui Huang

IPC分类号： H01L21/50 ,  H01L23/522

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.

摘要翻译： 一种集成电路封装系统的制造方法，包括：在第一外部连接层上形成第一级触点; 在第二外部连接电平旁边的第二外部连接电平上形成第二电平触点; 附接设备邻近第一级触点和第二级触点; 将第一级装置连接器附接到第一级触点和装置; 将第二级设备连接器附接到所述第二级接触器和所述设备; 以及在所述第一级触点，所述第二级触点，所述第一级装置连接器和所述第二级装置连接器上形成密封剂。

公开(公告)号：US20100090350A1

公开(公告)日：2010-04-15

申请号：US12248878

申请日：2008-10-09

申请人： Seng Guan Chow ,  Heap Hoe Kuan ,  Rui Huang

发明人： Seng Guan Chow ,  Heap Hoe Kuan ,  Rui Huang

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a multi-chip package system that includes: providing a package substrate; attaching a base semiconductor die to the package substrate; connecting an interconnect between the base semiconductor die and the package substrate; and encapsulating at least portions of the package substrate, the base semiconductor die, and the interconnect with an encapsulant defining a support protrusion adjacent to the interconnect and substantially perpendicular to the package substrate, a cavity bounded by the support protrusion, and a gap linking the cavity to the edge of the encapsulant.

摘要翻译： 本发明提供一种多芯片封装系统，其包括：提供封装基板; 将基底半导体管芯附接到封装衬底; 连接所述基底半导体管芯和所述封装衬底之间的互连; 以及将封装衬底，基底半导体管芯和互连件的至少一部分封装在与所述互连件相邻并且基本上垂直于所述封装衬底的限定支撑突起的密封剂上，由所述支撑突起限定的空腔以及将 空腔到密封剂的边缘。

公开(公告)号：US20100078828A1

公开(公告)日：2010-04-01

申请号：US12239774

申请日：2008-09-27

申请人： Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81365 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit package system includes: providing a mountable structure having a contact pad and an inner pad; mounting an integrated circuit device having a linear through channel over the mountable structure with the linear through channel traversing between an integrated circuit device first side and an integrated circuit device second side; and connecting the linear through channel exposed on the integrated circuit device second side to the inner pad.

摘要翻译： 集成电路封装系统包括：提供具有接触焊盘和内部焊盘的可安装结构; 在集成电路器件第一侧和集成电路器件第二侧之间穿过线性通道，将具有线性通道的集成电路器件安装在可安装结构上; 并将暴露在集成电路器件第二侧的线性通道连接到内部焊盘。

公开(公告)号：US07666709B1

公开(公告)日：2010-02-23

申请号：US12332077

申请日：2008-12-10

申请人： Yaojian Lin ,  Rui Huang ,  Hin Hwa Goh

发明人： Yaojian Lin ,  Rui Huang ,  Hin Hwa Goh

IPC分类号： H01L21/44

CPC分类号： H01L23/291 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L2221/68381 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has an adhesive layer depositing over a temporary carrier. A plurality of fiduciary patterns is formed over the adhesive layer. A repassivation layer is formed over semiconductor die. The repassivation layer may be a plurality of discrete regions. Alignment slots are formed in the repassivation layer. The fiducial patterns and alignment slots have slanted sidewalls. Leading with the repassivation layer, the semiconductor die is placed onto the carrier so that the alignment slots envelope and lock to the fiducial patterns. Alternatively, a die without the repassivation layer is placed between the fiducial patterns. An encapsulant is deposited over the semiconductor die while the die remain locked to the fiducial patterns. The carrier, adhesive layer, and fiducial patterns are removed after depositing the encapsulant. An interconnect structure is formed over the repassivation layer to electrically connect to contact pads on the semiconductor die.

摘要翻译： 半导体器件具有在临时载体上沉积的粘合剂层。 在粘合剂层上形成多个受信图案。 在半导体管芯上形成再钝化层。 再活化层可以是多个离散区域。 对准槽形成在再钝化层中。 基准图案和对准槽具有倾斜的侧壁。 通过再钝化层引导，将半导体管芯放置在载体上，使得对准槽包围并锁定到基准图案上。 或者，没有再钝化层的管芯被放置在基准图案之间。 在芯片保持锁定到基准图案的同时，在半导体管芯上沉积密封剂。 在沉积密封剂之后，除去载体，粘合剂层和基准图案。 在再钝化层上形成互连结构以电连接到半导体管芯上的接触焊盘。

公开(公告)号：US07576414B2

公开(公告)日：2009-08-18

申请号：US11934654

申请日：2007-11-02

申请人： Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

发明人： Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L23/20 ,  H01L21/00

CPC分类号： H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/10122 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48599 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage.

摘要翻译： 半导体器件具有在其上形成有多个有源器件的衬底。 在基板上形成接触垫。 在接触焊盘上形成焊料凸块。 在接触焊盘上形成静电放电（ESD）突起电极。 ESD凸块电极具有尖端。 ESD凸块电极由金制成。 芯片载体衬底具有冶金地连接到焊料凸块的接触垫。 芯片载体衬底也具有接地板。 接地板是低阻抗接地点。 根据有源器件的ESD灵敏度，ESD突起电极的尖端与接地板分开一段距离。 该距离由待保护的有源器件的ESD灵敏度的放电阈值电压与大气放电电压的比率确定。

公开(公告)号：USD995939S1

公开(公告)日：2023-08-15

申请号：US29894067

申请日：2023-06-06

申请人： Rui Huang

设计人： Rui Huang

摘要： FIG. 1 is a front, right and top perspective view of a bird feeder, showing my design.
FIG. 2 is a rear, left and bottom perspective view thereof.
FIG. 3 is a front elevation view thereof.
FIG. 4 is a rear elevation view thereof.
FIG. 5 is a left side elevation view thereof.
FIG. 6 is a right side elevation view thereof.
FIG. 7 is a top plan view thereof.
FIG. 8 is a bottom plan view thereof; and,
FIG. 9 is an enlarged view of detail 9 in FIG. 1.
The broken lines depict portions of the bird feeder that form no part of the claimed design. The dot-dash broken lines in FIGS. 1 and 9 depict the boundaries of the enlargements that form no part of the claimed design.