公开(公告)号：US06402970B1

公开(公告)日：2002-06-11

申请号：US09643213

申请日：2000-08-22

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01B1300

CPC classification number: H05K3/4007 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  Y10S205/92 ,  Y10T29/49128 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A method of manufacturing a support circuit includes providing a conductive layer with top and bottom surfaces, providing a top etch mask on the top surface that includes an opening that exposes a portion of the top surface, providing a bottom etch mask on the bottom surface that includes an opening that exposes a portion of the bottom surface, applying an etch to the exposed portion of the top surface through the opening in the top etch mask, thereby etching partially but not completely through the conductive layer and forming a recessed portion in the conductive layer below the top surface, forming an insulative base on the recessed portion without forming the insulative base on the top surface, and applying an etch to the exposed portion of the bottom surface through the opening in the bottom etch mask, thereby forming a through-hole in the recessed portion that extends to and is covered by the insulative base.

Abstract translation: 制造支撑电路的方法包括：提供具有顶表面和底表面的导电层，在顶表面上提供顶部蚀刻掩模，该掩模包括暴露顶表面的一部分的开口，在底表面上提供底蚀刻掩模， 包括露出底表面的一部分的开口，通过顶部蚀刻掩模中的开口对顶表面的暴露部分施加蚀刻，从而通过导电层部分蚀刻但不完全蚀刻，并在导电层中形成凹陷部分 在顶表面下方形成绝缘基底，而不在顶表面上形成绝缘基底，并且通过底蚀刻掩模中的开口对底表面的暴露部分施加蚀刻，从而形成通孔， 在凹部中延伸并被绝缘基底覆盖的孔。

公开(公告)号：US06350386B1

公开(公告)日：2002-02-26

申请号：US09665931

申请日：2000-09-20

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L21302

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L23/49861 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S205/92 ,  Y10T29/49128 ,  Y10T29/49156 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of manufacturing a support circuit includes providing a conductive layer with top and bottom surfaces, providing a top etch mask on the top surface that includes an opening that exposes a portion of the top surface, providing a bottom etch mask on the bottom surface that includes an opening that exposes a portion of the bottom surface, applying an etch to the exposed portion of the top surface through the opening in the top etch mask thereby etching partially but not completely through the conductive layer and forming a recessed portion in the conductive layer below the top surface, forming an insulative base on the recessed portion without forming the insulative base on the top surface, applying an etch to the exposed portion of the bottom surface through the opening in the bottom etch mask thereby forming a routing line in the recessed portion, applying an etch to the insulative base to form an opening in the insulative base that exposes a portion of the routing line, and applying an etch to the exposed portion of the routing line through the opening in the insulative base thereby forming an opening in the routing line with tapered sidewalls. The method may also include providing an adhesive beneath the support circuit, and applying an etch that enlarges the opening in the insulative base to expose a portion of a top surface of the routing line adjacent to the opening in the routing line and that forms an opening in the adhesive beneath the opening in the routing line.

Abstract translation: 制造支撑电路的方法包括：提供具有顶表面和底表面的导电层，在顶表面上提供顶部蚀刻掩模，该掩模包括暴露顶表面的一部分的开口，在底表面上提供底蚀刻掩模， 包括露出底表面的一部分的开口，通过顶部蚀刻掩模中的开口对顶表面的暴露部分施加蚀刻，从而部分蚀刻但不完全地通过导电层蚀刻，并在导电层中形成凹陷部分 在顶表面下方，在凹部上形成绝缘基底，而不在顶表面上形成绝缘基底，通过底蚀刻掩模中的开口对底表面的暴露部分施加蚀刻，从而在凹陷部分中形成布线线 对所述绝缘基底施加蚀刻，以在所述绝缘基体中形成露出所述布线线的一部分的开口，并且 通过绝缘基体中的开口对路线的暴露部分进行蚀刻，从而在具有锥形侧壁的布线线中形成开口。 该方法还可以包括在支撑电路下方提供粘合剂，以及施加一种蚀刻，其扩大绝缘基体中的开口，以暴露与布线线中的开口相邻的布线线的顶表面的一部分，并形成开口 在路线中的开口下面的粘合剂中。

公开(公告)号：US5167992A

公开(公告)日：1992-12-01

申请号：US667778

申请日：1991-03-11

Applicant: Charles W. C. Lin ,  Ian Y. K. Yee

Inventor： Charles W. C. Lin ,  Ian Y. K. Yee

IPC: C23C18/16 ,  H05K3/24

CPC classification number: H05K3/244 ,  C23C18/1608 ,  C23C18/1635 ,  C23C18/1889 ,  C23C18/2006 ,  C23C18/208 ,  C23C18/32 ,  C23C18/42 ,  H05K2201/0347 ,  H05K2201/0761 ,  H05K2203/0392 ,  H05K2203/095

Abstract: A method for electrolessly plating an overcoat metal on a metal conductor disposed on a dielectric surface of a substrate. The method includes removing carbonized film from the dielectric surface by applying a plasma discharge, acid treating the metal conductor by dipping the substrate in a first acid solution in order to clean the surface of the metal conductor, activating the metal conductor to allow electroless plating thereon by dipping the substrate in a metal activator solution, deactivating the dielectric surface to prevent electroless plating thereon without deactivating the metal conductor by dipping the substrate in a second acid solution, and plating an overcoat metal on the metal conductor by dipping the substrate in an electroless plating solution so that the overcoat metal plates on and coats the metal conductor without plating on the dielectric surface.

Abstract translation: 在设置在基板的电介质表面上的金属导体上无电镀电镀金属的方法。 该方法包括通过施加等离子体放电来从电介质表面去除碳化膜，通过将基底浸渍在第一酸溶液中来酸化处理金属导体，以清洁金属导体的表面，激活金属导体以允许金属导体在其上进行无电镀 通过将基底浸渍在金属活化剂溶液中，使电介质表面失活以防止其上化学镀，而不使金属导体通过将基底浸渍在第二酸溶液中而使金属导体失活，并且通过将基底浸渍在无电镀中而在金属导体上镀覆外涂层金属 电镀溶液，使得外涂金属板在金属导体上涂覆并涂覆在电介质表面上。

公开(公告)号：US5116463A

公开(公告)日：1992-05-26

申请号：US717767

申请日：1991-06-19

Applicant: Charles W. C. Lin ,  Randy L. German ,  Ian Y. K. Yee ,  David M. Sigmond

Inventor： Charles W. C. Lin ,  Randy L. German ,  Ian Y. K. Yee ,  David M. Sigmond

IPC: H01L21/48 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/422 ,  H01L21/4846 ,  H01L21/486 ,  H05K2203/163 ,  H05K3/4644

Abstract: A method for detecting the completion of electrolessly depositing metal into a via. The method includes providing a non-autocatalytic detection mask with an opening over a via containing an autocatalytic material, electrolessly depositing a conductive metal into the via which fails to plate to the mask, and continuing the deposition until metal in the via contacts the mask, at which time the electrochemical potential of the mask changes and the metal plates to and covers the entire mask. The completion of the electroless via fill can be detected by changes in both the appearance and electrochemical potential of the mask.

Abstract translation: 一种用于检测无电沉积金属到通孔中的完成方法。 该方法包括提供非自动催化检测掩模，该通孔包含含有自催化材料的通孔，将导电金属无电沉积到通孔中，该通孔不能平铺于掩模上，并且继续沉积，直到通孔中的金属接触掩模， 此时，掩模的电化学电位改变，金属板覆盖整个掩模。 可以通过掩模的外观和电化学电位的变化来检测无电通孔填充物的完成。

公开(公告)号：US4952275A

公开(公告)日：1990-08-28

申请号：US452458

申请日：1989-12-15

Applicant: Charles W. C. Lin ,  Ian Y. K. Yee

Inventor： Charles W. C. Lin ,  Ian Y. K. Yee

IPC: C23F1/10

CPC classification number: C23F1/10

Abstract: A process and solution for selectively etching copper. The etching is effected by a nonaqueous solution of dimethyl sulfoxide and a halocarbon compound.

Abstract translation: 一种选择性蚀刻铜的工艺和解决方案。 蚀刻由二甲基亚砜和卤代烃化合物的非水溶液进行。

公开(公告)号：US08531024B2

公开(公告)日：2013-09-10

申请号：US13091162

申请日：2011-04-21

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L23/34 ,  H01L23/10 ,  H01L33/00

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/0204 ,  H05K1/115 ,  H05K3/0061 ,  H05K3/06 ,  H05K2201/09054 ,  H05K2201/09509 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01007 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/00012

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace, a substrate and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal, a conductive pattern and first and second vias. The substrate includes the conductive pattern and a dielectric layer. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive and an aperture in the substrate, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the conductive pattern and the vias.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线，衬底和粘合剂。 散热器包括一个柱子和一个底座。 导电迹线包括焊盘，端子，导电图案以及第一和第二通孔。 基板包括导电图案和电介质层。 半导体器件电连接到导电迹线并热连接到散热器。 柱从基部向上延伸到粘合剂中的开口和基底中的孔，并且基部从柱横向延伸。 导电迹线使用导电图案和通孔提供焊盘和端子之间的信号路由。

公开(公告)号：US08298868B2

公开(公告)日：2012-10-30

申请号：US13079044

申请日：2011-04-04

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/00 ,  H01L23/12

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal, a plated through-hole and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 一种制造半导体芯片组件的方法包括提供柱和基座，在基底上安装粘合剂，包括将柱插入粘合剂中的开口中，将导电层安装在粘合剂上，包括使导柱与导电 然后使粘合剂在柱和导电层之间向上流动，固化粘合剂，然后提供包括衬垫，端子，电镀通孔和导电层的选定部分的导电迹线，安装半导体器件 在支柱上，其中散热器包括柱和基座，将半导体器件电连接到导电迹线并将半导体器件热连接到散热器。

公开(公告)号：US08241962B2

公开(公告)日：2012-08-14

申请号：US12834014

申请日：2010-07-12

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L21/603

CPC classification number: H01L33/486 ,  H01L21/486 ,  H01L23/3677 ,  H01L23/5389 ,  H01L33/642 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of making a semiconductor chip assembly includes providing a thermal post, a signal post and a base, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a conductive layer on the adhesive including aligning the thermal post with a first aperture in the conductive layer and the signal post with a second aperture in the conductive layer, then flowing the adhesive upward between the thermal post and the conductive layer and between the signal post and the conductive layer, solidifying the adhesive, providing a conductive trace that includes a pad, a terminal and the signal post, wherein the pad includes a selected portion of the conductive layer, mounting a semiconductor device on the thermal post, wherein a heat spreader includes the thermal post and the base and the semiconductor device extends into a cavity in the thermal post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 制造半导体芯片组件的方法包括提供热柱，信号柱和基座，将粘合剂安装在基座上，包括将热柱插入粘合剂中的第一开口中，并将信号柱插入粘合剂中的第二开口中 将导电层安装在粘合剂上，包括将热柱与导电层中的第一孔对准，并且将信号柱与导电层中的第二孔对准，然后使粘合剂在热柱和导电层之间以及在导电层之间向上流动 信号柱和导电层，固化粘合剂，提供包括焊盘，端子和信号柱的导电迹线，其中焊盘包括导电层的选定部分，将半导体器件安装在热柱上，其中 散热器包括热柱和基座，并且半导体器件延伸到热柱中的空腔中，电连接 半导体器件到导电迹线并将半导体器件热连接到散热器上。

公开(公告)号：US08236618B2

公开(公告)日：2012-08-07

申请号：US13004881

申请日：2011-01-12

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/00 ,  H01L23/12

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L33/486 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85205 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0369 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives and a base, wherein the first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad and a terminal, wherein the pad extends beyond the base in the first vertical direction and the terminal extends beyond the base in the second vertical direction, providing a heat spreader that includes the posts and the base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 制造半导体芯片组件的方法包括提供第一和第二柱，第一和第二粘合剂和基底，其中第一柱从第一垂直方向上的基部延伸到第一粘合剂中的第一开口中，第二柱从 将基部在第二垂直方向上插入到第二粘合剂中的第二开口中，并且基座夹在柱之间并从支柱横向延伸，然后使第一粘合剂沿第一垂直方向流动，使第二粘合剂沿第二垂直方向流动， 粘合剂，然后提供包括垫和端子的导电迹线，其中所述垫在所述第一垂直方向上延伸超出所述基部，并且所述端子在所述第二垂直方向上延伸超出所述基部，从而提供包括所述柱和 然后将半导体器件安装在第一柱上，将半导体器件电连接到导电迹线上 将半导体器件热连接到散热器上。

公开(公告)号：US08207553B2

公开(公告)日：2012-06-26

申请号：US12714421

申请日：2010-02-26

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L33/00 ,  H01L23/34

CPC classification number: H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L33/483 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a base. A cavity extends through the adhesive into the base. The semiconductor device extends into the cavity, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The adhesive extends between the cavity and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括一个底座。 空腔通过粘合剂延伸到基座中。 半导体器件延伸到腔中，电连接到导电迹线并且热连接到散热器。 粘合剂在空腔和导电迹线之间以及基底和导电迹线之间延伸。 导电迹线位于腔体外部，并提供焊盘和端子之间的信号路由。