公开(公告)号：US20210098059A1

公开(公告)日：2021-04-01

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/56 ,  G11C7/10 ,  G06F3/06

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US10748602B2

公开(公告)日：2020-08-18

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel H. Morris ,  Kaushik Vaidyanathan ,  Niloy Mukherjee ,  Dmitri E. Nikonov ,  Ian Young ,  Tanay Karnik

IPC: G11C11/00 ,  G11C11/413 ,  G11C11/412 ,  G11C7/10 ,  G11C13/00 ,  G11C14/00 ,  G11C7/20

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20200152781A1

公开(公告)日：2020-05-14

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US20190386661A1

公开(公告)日：2019-12-19

申请号：US15779074

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H03K19/18 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US10439599B2

公开(公告)日：2019-10-08

申请号：US14864241

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K3/03 ,  G06K9/00

Abstract: Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.

公开(公告)号：US09926193B2

公开(公告)日：2018-03-27

申请号：US15301337

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Jorge A. Munoz ,  Dmitri E. Nikonov ,  Kelin J. Kuhn ,  Patrick Theofanis ,  Chytra Pawashe ,  Kevin Lin ,  Seiyon Kim

IPC: B82B1/00 ,  B82B3/00 ,  H01L29/66 ,  H01L29/84 ,  H01L29/82 ,  H01H59/00 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00

CPC classification number: B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

公开(公告)号：US20170323928A1

公开(公告)日：2017-11-09

申请号：US15658078

申请日：2017-07-24

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Dmitri E. Nikonov ,  Robert S. Chau

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  G11C19/00

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/08

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.

公开(公告)号：US20170287979A1

公开(公告)日：2017-10-05

申请号：US15508430

申请日：2014-09-25

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Asif Khan ,  Raseong KIM ,  Tahir Ghani ,  Ian A. Young

IPC: H01L27/22 ,  H01L43/02 ,  H01L41/20 ,  H01L27/20 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/20 ,  H01L28/55 ,  H01L41/20 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

公开(公告)号：US09583566B2

公开(公告)日：2017-02-28

申请号：US14942274

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L29/06 ,  H01L29/772 ,  H01L29/267 ,  H01L29/739 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/775

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract translation: 一个实施例包括一个包括源极，沟道和漏极的异质结隧道场效应晶体管; 其中（a）所述通道包括对应于通道长度的长轴和对应于通道宽度并与所述长轴正交的短轴; （b）通道长度小于10nm; （c）源极掺杂第一极性并具有第一导带; （d）漏极掺杂有与第一极性相反的第二极性，并且漏极具有比第一导带具有更高能量的第二导带。 本文描述了其它实施例。

公开(公告)号：US20160284406A1

公开(公告)日：2016-09-29

申请号：US14668896

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Dmitri E. Nikonov ,  Elijah V. Ilya Karpov ,  Ian A. Young ,  Robert S. Chau

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/4116 ,  G11C11/412 ,  G11C11/413 ,  G11C11/416 ,  G11C11/419 ,  G11C13/0097

Abstract: An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.

Abstract translation: 提供了一种装置，其包括：具有集成在该SRAM单元内的至少两个非易失性（NV）电阻存储器元件的静态随机存取存储器（SRAM）单元; 以及将存储在SRAM单元中的数据自存储到至少两个NV电阻存储器元件的第一逻辑。 提供了一种方法，其包括当施加到SRAM单元的电压降低到阈值电压时执行自存储操作，以将SRAM单元的电压状态存储到至少两个NV电阻存储器元件，其中至少两个NV 电阻存储元件与SRAM单元集成; 以及当通过将来自所述至少两个NV电阻性存储器元件的数据复制到所述SRAM单元的存储节点的情况下，施加到所述SRAM单元的电压增加到阈值电压时，执行自恢复操作。