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    Lightly donor doped electrodes for high-dielectric-constant materials
    72.
    发明授权
    Lightly donor doped electrodes for high-dielectric-constant materials 失效

    公开(公告)号：US06204069B1

    公开(公告)日：2001-03-20

    申请号：US08317108

    申请日：1994-10-03

    申请人： Scott R. Summerfelt ,  Howard R. Beratan ,  Bruce Gnade

    发明人： Scott R. Summerfelt ,  Howard R. Beratan ,  Bruce Gnade

    IPC分类号： H01L2100

    CPC分类号： H01G4/008 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/56 ,  Y10S257/917 ,  Y10T29/43 ,  Y10T29/435

    摘要： A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions. The lightly donor doped perovskite can be deposited and etched by effectively the same techniques that are developed for the high-dielectric-constant material. The same equipment may used to deposit and etch both the perovskite electrode and the dielectric. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.

    Stable high-dielectric-constant material electrode and method
    73.
    发明授权
    Stable high-dielectric-constant material electrode and method 有权
    稳定的高介电常数材料电极及方法

    公开(公告)号：US6117689A

    公开(公告)日：2000-09-12

    申请号：US217758

    申请日：1998-12-21

    申请人： Scott R. Summerfelt

    发明人： Scott R. Summerfelt

    IPC分类号： H01L21/02 ,  H01L21/3205 ,  H01L21/70

    CPC分类号： H01L28/60 ,  H01L21/32051

    摘要： A structure for, and method of forming, an oxygen diffusion resistant electrode for high-dielectric-constant materials is disclosed. The electrode comprises a single grain of an oxygen stable material over a barrier layer. The single crystal oxygen stable layer is generally substantially impervious to oxygen diffusion at all relevant deposition and annealing temperatures. The disclosed structure is an integrated circuit comprising an array of microelectronic structures, with each of the microelectronic structures comprising an oxidizable layer (e.g., polysilicon 50), a barrier layer (e.g. TiN 64) overlying the oxidizable layer, a single crystal oxygen stable layer (e.g., Pt 98) overlying the barrier layer, and a high-dielectric-constant material layer (e.g., barium strontium titanate 36) overlying the oxygen stable layer. The disclosed method of fabricating an integrated circuit comprises forming an array of microelectronic structures, wherein forming each of said microelectronic structures comprises forming a barrier layer on an oxidizable layer, depositing a single crystal oxygen stable layer on the barrier layer, and depositing a high-dielectric-constant material layer on the oxygen stable layer. The single crystal oxygen stable layer prevents oxidation of the barrier layer and the oxidizable layer during subsequent processing.

    摘要翻译： 公开了用于高介电常数材料的氧扩散阻止电极的结构和形成方法。 电极在阻挡层上包括单一的氧稳定材料晶粒。 在所有相关沉积和退火温度下，单晶氧稳定层通常基本上不渗透氧气扩散。 所公开的结构是包括微电子结构阵列的集成电路，其中每个微电子结构包括可氧化层（例如，多晶硅50），覆盖在可氧化层上的阻挡层（例如TiN 64），单晶氧稳定层 （例如Pt 98）和覆盖在氧稳定层上的高介电常数材料层（例如，钛酸钡锶36）。 所公开的制造集成电路的方法包括形成微电子结构的阵列，其中形成每个所述微电子结构包括在可氧化层上形成阻挡层，在阻挡层上沉积单晶氧稳定层， 氧稳定层上的介电常数材料层。 单晶氧稳定层防止在后续处理期间阻挡层和可氧化层的氧化。

    Heteroepitaxy by large surface steps
    75.
    发明授权
    Heteroepitaxy by large surface steps 失效
    通过大面积台阶进行异质外延

    公开(公告)号：US6083812A

    公开(公告)日：2000-07-04

    申请号：US12556

    申请日：1993-02-02

    申请人： Scott R. Summerfelt

    发明人： Scott R. Summerfelt

    IPC分类号： C30B25/18 ,  C30B33/06 ,  H01L21/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/34

    CPC分类号： H01L29/66969 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/0445 ,  Y10S438/931

    摘要： A method for heteroepitaxial growth and the device wherein a single crystal ceramic substrate, preferably Y stabilized zirconia, MgAl.sub.2 O.sub.4, A1.sub.2 O.sub.3, 3C--SiC, 6H--SiC or MgO is cut and polished at from about 1.0 to about 10 degrees off axis to produce a substantially flat surface. The atoms on the surface are redistributed on the surface to produce surface steps of at least three lattice spacings. An optional epitaxially grown ceramic buffer layer, preferably AlN or GaN, is then formed on the substrate. Then a layer of semiconductor, preferably SiC, AlN when the buffer layer is used and is not AlN or GaN is grown over the substrate and buffer layer, if used.

    摘要翻译： 用于异质外延生长的方法和其中将单晶陶瓷衬底，优选Y稳定的氧化锆，MgAl 2 O 4，A 12 O 3，3C-SiC，6H-SiC或MgO在离轴上约1.0至约10度切割和抛光的装置，以产生 基本平坦的表面。 表面上的原子重新分布在表面上以产生至少三个晶格间距的表面步骤。 然后在衬底上形成任选的外延生长的陶瓷缓冲层，优选AlN或GaN。 然后，如果使用缓冲层，并且不是AlN或GaN，则半导体层，优选SiC，AlN生长在衬底和缓冲层上。

    Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
    77.
    发明授权
    Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer 失效
    含有Pb / Bi的高介电常数氧化物，使用非Pb / Bi的钙钛矿作为缓冲层

    公开(公告)号：US5650646A

    公开(公告)日：1997-07-22

    申请号：US395016

    申请日：1995-02-27

    申请人： Scott R. Summerfelt

    发明人： Scott R. Summerfelt

    IPC分类号： C23C14/08 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H05K1/03 ,  H01L29/76

    CPC分类号： H01L21/28185 ,  H01L21/02197 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/314 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  Y10S148/014 ,  Y10S148/118 ,  Y10S438/967

    摘要： This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick. A second non-Pb/Bi-containing high-dielectric constant oxide layer 30 may be grown on top of the Pb/Bi-containing high-dielectric constant oxide and a conducting layer (top electrode 32) may also be grown on the second non-Pb/Bi-containing high-dielectric constant oxide layer.

    摘要翻译： 这是用于制造在半导体电路中有用的结构的方法。 该方法包括：在半导体衬底上直接或间接生长非Pb / Bi的高介电常数氧化物层的缓冲层; 以及在所述缓冲层上沉积含Pb / Bi的高介电常数氧化物。 或者，这可以是在半导体电路中有用的结构，其包括：直接或间接地在半导体衬底10上的非含铅高介电常数氧化物层的缓冲层26; 和在缓冲层上的含铅高介电常数氧化物28。 优选地，在半导体衬底上外延生长锗层12，并且在锗层上生长缓冲层。 当衬底是硅时，非Pb / Bi的高介电常数氧化物层的厚度优选小于约10nm。 可以在含Pb / Bi的高介电常数氧化物的顶部上生长第二非Pb / Bi的高介电常数氧化物层30，并且还可以在第二非绝缘材料上生长导电层（顶电极32） -Pb / Bi高介电常数氧化物层。

    Structure and method including dry etching techniques for forming an array of thermal sensitive elements
    78.
    发明授权
    Structure and method including dry etching techniques for forming an array of thermal sensitive elements 失效
    包括用于形成热敏元件阵列的干蚀刻技术的结构和方法

    公开(公告)号：US5647946A

    公开(公告)日：1997-07-15

    申请号：US463170

    申请日：1995-06-05

    申请人： James F. Belcher ,  Howard R. Beratan ,  Scott R. Summerfelt

    发明人： James F. Belcher ,  Howard R. Beratan ,  Scott R. Summerfelt

    IPC分类号： G01J1/02 ,  G01J5/34 ,  H01L21/302 ,  H01L21/3065 ,  H01L27/14 ,  H01L37/02 ,  H01L21/00

    CPC分类号： H01L37/02 ,  G01J5/34 ,  Y10S438/942

    摘要： An array of thermal sensor elements (16) is formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of metal contacts (60) is formed to define masked (61) and unmasked (68) regions of the substrate (46). A second layer of metal contacts (62) is formed on the first layer of contacts (60). A radiation etch mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). A dry-etch mask layer (74) is formed to encapsulate the exposed portions of the first layer of contacts (60) and radiation etch mask layer (66). An initial portion of each unmasked region (68) is etched using a dry-etch process. The remaining portions of the unmasked regions (68) are exposed to an etchant (70) and irradiated with electromagnetic energy to substantially increase the reactivity between the remaining portions and the etchant (70). During such irradiation, the etchant (70) etches the remaining portions substantially faster than the first layer of contacts (60) and the radiation etch mask layer (66).

    摘要翻译： 一组热传感器元件（16）由具有红外线吸收器和附接到其上的公共电极组件（18）的热电基片（46）形成。 第一层金属触点（60）被形成以限定衬底（46）的掩模（61）和未屏蔽（68）区域。 第二层金属触点（62）形成在第一层触点（60）上。 形成辐射蚀刻掩模层（66）以封装第二层触点（62）的暴露部分。 形成干蚀刻掩模层（74）以封装第一层触点（60）和辐射蚀刻掩模层（66）的暴露部分。 使用干蚀刻工艺蚀刻每个未掩模区域（68）的初始部分。 未掩蔽区域（68）的剩余部分暴露于蚀刻剂（70）并用电磁能照射，以显着增加其余部分和蚀刻剂（70）之间的反应性。 在这种照射期间，蚀刻剂（70）基本上比第一层触点（60）和辐射蚀刻掩模层（66）更快地蚀刻剩余部分。