公开(公告)号：US20200006219A1

公开(公告)日：2020-01-02

申请号：US16258672

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming-Shih Yeh

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31 ,  H01L21/56 ,  H01L21/822 ,  H01L25/10 ,  H01L25/00

Abstract: A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.

公开(公告)号：US10153205B2

公开(公告)日：2018-12-11

申请号：US14990976

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Jui-Pin Hung ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L21/78 ,  H01L49/02 ,  H01L27/12 ,  H01L27/32 ,  H01L23/00 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/525

Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.

公开(公告)号：US20170345741A1

公开(公告)日：2017-11-30

申请号：US15201604

申请日：2016-07-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsi Wu ,  Chun-Yi Liu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Shih-Peng Tai ,  Chuen-De Wang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49527 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/4952 ,  H01L23/49589 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19011

Abstract: An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die.

公开(公告)号：US20240421111A1

公开(公告)日：2024-12-19

申请号：US18506747

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/00

Abstract: A package device includes a top die having a top interconnect structure on a first surface of a transistor layer and a bottom interconnect structure on a second surface of the transistor layer. One of the top interconnect structure or the bottom interconnect structure is direct bonded onto a bottom die. The bottom interconnect structure includes a power rail which directly contacts transistor contacts that are directly contacting a transistor structure in the transistor layer.

公开(公告)号：US20240282743A1

公开(公告)日：2024-08-22

申请号：US18654268

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L25/105 ,  H01L24/03 ,  H01L24/11 ,  H01L24/20 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13019 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/27462 ,  H01L2224/29026 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81121 ,  H01L2224/81125 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/8191 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

公开(公告)号：US12020953B2

公开(公告)日：2024-06-25

申请号：US18297897

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Wei-Yu Chen

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49503 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/28 ,  H01L25/18 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

公开(公告)号：US20240088104A1

公开(公告)日：2024-03-14

申请号：US18517232

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/50 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81385 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

公开(公告)号：US11848271B2

公开(公告)日：2023-12-19

申请号：US17366575

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chen-Hua Yu

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20230245923A1

公开(公告)日：2023-08-03

申请号：US18298780

申请日：2023-04-11

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L21/768 ,  H01L23/3128 ,  H01L24/19 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2224/14135 ,  H01L2224/83104 ,  H01L2224/83005 ,  H01L21/568

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

公开(公告)号：US20230207531A1

公开(公告)日：2023-06-29

申请号：US18175189

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L21/568 ,  H01L25/105 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/3675 ,  H01L21/4853 ,  H01L2225/06548 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/181 ,  H01L2924/15311 ,  H01L2224/80904 ,  H01L24/03

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.